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PD17134A SUBSERIES
4-BIT SINGLE-CHIP MICROCONTROLLER
PD17134A PD17135A PD17136A PD17137A PD17P136A PD17P137A
(c)
1993
Document No. U11607EJ3V0UM00 (3rd edition) Date Published December 1996 N Printed in Japan
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Regional Information
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J96. 8
SIMPLEHOST is a trademark of NEC Corp.
MS-DOS and Windows are trademarks of Microsoft Corp. PC/AT and PC DOS are trademarks of IBM Corp.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M7 96.5
Major Revisions in This Edition
Page Throughout p. 5 p. 18 Description Change of name PD1713XA to PD17134A subseries Correction of (2) Program memory write/verify mode in 1.4 PIN CONFIGURATION Change of Figure 3-2 Value of Program Counter after Instruction Partial correction of 3.2.2 On Execution of Branch Instruction (BR) Partial correction of 3.2.3 On During Execution of Subroutine Call Change of CHAPTER 4 PROGRAM MEMORY (ROM) Partial correction of Figure 5-1 Data Memory Configuration Change of CHAPTER 6 STACK Partial correction of 7.2.2 Address Register Functions Change of 7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP) Partial change of 7.6.2 Functions of General Register Pointer Partial change of 7.7.1 Program Status Word Configuration Change of 7.7.4 Zero Flag (Z) and Compare Flag (CMP) Partial correction of 7.7.5 Carry Flag (CY) Partial correction of 9.2.3 Register File Manipulation Instructions Change of CHAPTER 13 PERIPHERAL HARDWARE Change of CHAPTER 14 INTERRUPT FUNCTIONS Change of CHAPTER 16 STANDBY FUNCTION Change of CHAPTER 17 RESET Partial change of Table 18-2 Differences between Mask ROM Version and OneTime PROM Version Partial change of 19.3 LIST OF THE INSTRUCTION SET Partial change of 19.5 INSTRUCTIONS Change of CHAPTER 20 ASSEMBLER RESERVED WORDS Partial change of 20.2 RESERVED SYMBOLS Addition of APPENDIX A DEVELOPMENT OF PD171xx SUBSERIES Addition of APPENDIX B COMPARISON OF FUNCTIONS BETWEEN PD17135A, 17137A, AND PD17145 SUBSERIES Addition of APPENDIX D NOTES ON CONFIGURATION OF SYSTEM CLOCK OSCILLATION CIRCUIT The mark shows major revisions made in this edition.
p. 19 p. 23 p. 31 p. 35 p. 43 p. 47
p. 58 p. 59 p. 61 p. 61 p. 71 p. 111 p. 149 p. 169 p. 179 p. 190
p. 194 p. 198 p. 255 p. 257 p. 261 p. 263
p. 267
PREFACE
Target
: This manual is intended for user engineers who understand the functions of each product in the PD17134A subseries and try to design application systems using the PD17134A subseries.
Purpose
: The purpose of this manual is for the user to understand the hardware functions of the
PD17134A subseries.
Use : The manual assumes that the reader has a general knowledge of electricity, logic circuits, microcomputers. * To understand the functions of the PD17134A subseries in a general way; Read the manual from CONTENTS. * To look up instruction functions in detail when you know the mnemonic of an instruction; Use APPENDIX E INSTRUCTION LIST. * To look up an instruction when you do not know its mnemonic but know outlines of the function; Refer to 19.3 LIST OF THE INSTRUCTION SET for search for the mnemonic of the instruction, then see 19.5 INSTRUCTIONS for the functions. * To learn the electrical specifications of the PD17134A subseries Refer to the Data Sheet available separately. * To learn the application examples of the functions of the PD17134A subseries Refer to the Application Note available separately. Legend : Data representation weight : High-order and low-order digits are indicated from left to right. Active low representation Memory map address Note Caution Remark Number representation : xxx (pin or signal name is overlined) : Top: low-order, bottom: high-order : Explanation of Note in the text : Caution to which you should pay attention : Supplementary explanation to the text : Binary number Decimal number ...xxxx or xxxxB ...xxxx
Hexadecimal number ...xxxxH
Related Documents : The following documents are provided for the PD17134A subseries. The numbers listed in the table are the document numbers.
Product name
PD17134A
Document name Brochure Data sheet User's manual Application note IE-17K (Ver. 1.6) user's manual IE-17K-ET (Ver. 1.6) user's manual SE board user's manual IF-1166 U10591E
PD17135A
IF-1169 U10592E
PD17136A
IF-1166 U10591E
PD17137A
IF-1169 U10592E
PD17P136A
IF-1168 IC-2871
PD17P137A
IF-1165 IC-2872
IEU-1369 IEA-1297 (Introduction), IEA-1293 (Rice cooker, thermos bottle) EEU-1467
EEU-1466
EEU-1379
SIMPLEHOSTTM user's manual
AS17K assembler user's manual Device file user's manual
EEU-1336 (Introduction), EEU-1337 (Reference)
EEU-1287
U10777E
Pin name and symbol name should be read according to the system clock type.
System clock RC oscillation PD17134A PD17136A PD17P136A OSC1 OSC0 System clock fCC Ceramic oscillation PD17135A PD17137A PD17P137A XIN XOUT fX
Pin name, symbol name Pin for system clock oscillation
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION ................................................................................................. 1
1.1 1.2 1.3 1.4 FUNCTION LIST ........................................................................................................................................ 2 ORDERING INFORMATION ..................................................................................................................... 3 BLOCK DIAGRAM .................................................................................................................................... 4 PIN CONFIGURATION (TOP VIEW) ........................................................................................................ 5
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 9
2.1 2.2 2.3 2.4 PIN FUNCTIONS ....................................................................................................................................... 9 PIN INPUT/OUTPUT CIRCUIT ............................................................................................................... 11 PROCESSING OF UNUSED PINS ......................................................................................................... 14 NOTES ON USING RESET PIN AND P1B0 PIN ................................................................................... 15
CHAPTER 3 PROGRAM COUNTER (PC) ........................................................................................... 17
3.1 3.2 PROGRAM COUNTER CONFIGURATION ............................................................................................ 17 PROGRAM COUNTER OPERATION ..................................................................................................... 17 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 At Reset ..................................................................................................................................... 18 During Execution of the Branch Instruction (BR) ..................................................................... 18 During Execution of Subroutine Calls (CALL) .......................................................................... 19 During Execution of Return Instructions (RET, RETSK, RETI) ............................................... 20 During Table Reference (MOVT) .............................................................................................. 20 During Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT, SKF) ...................... 21 When an Interrupt Is Received ................................................................................................. 21
CHAPTER 4
4.1 4.2
PROGRAM MEMORY (ROM).......................................................................................... 23
PROGRAM MEMORY CONFIGURATION ............................................................................................. 23 PROGRAM MEMORY USAGE ............................................................................................................... 24 4.2.1 4.2.2 Flow of the Program .................................................................................................................. 24 Table Reference ......................................................................................................................... 27
CHAPTER 5 DATA MEMORY (RAM) .................................................................................................... 31
5.1 DATA MEMORY CONFIGURATION ....................................................................................................... 31 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 System Register (SYSREG) ..................................................................................................... 32 Data Buffer (DBF) ...................................................................................................................... 32 General Register (GR) .............................................................................................................. 33 Port Registers ............................................................................................................................ 33 General Data Memory ............................................................................................................... 34 Unmounted Data Memory ......................................................................................................... 34
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CHAPTER 6
6.1 6.2 6.3 6.4 6.5 6.6
STACK .............................................................................................................................. 35
STACK CONFIGURATION ...................................................................................................................... 35 FUNCTIONS OF THE STACK ................................................................................................................ 35 ADDRESS STACK REGISTERS (ASRs) ............................................................................................... 36 INTERRUPT STACK REGISTERS (INTSKs) ........................................................................................ 36 STACK POINTER (SP) AND INTERRUPT STACK REGISTERS ........................................................ 37 STACK OPERATION ............................................................................................................................... 38 6.6.1 6.6.2 6.6.3 On Execution of Instructions CALL, RET, RETSK ................................................................... 38 Table Reference (MOVT DBF, @AR Instruction) ..................................................................... 38 Operation on Execution of Interrupt Receipt and RETI Instruction......................................... 39
6.7
STACK NESTING LEVELS AND THE PUSH AND POP INSTRUCTIONS ......................................... 39
CHAPTER 7 SYSTEM REGISTER (SYSREG) .................................................................................... 41
7.1 7.2 SYSTEM REGISTER CONFIGURATION ............................................................................................... 41 ADDRESS REGISTER (AR) ................................................................................................................... 43 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 Address Register Configuration ................................................................................................ 43 Address Register Functions ...................................................................................................... 43 Window Register Configuration ................................................................................................ 45 Window Register Functions ...................................................................................................... 45 Bank Register Configuration ..................................................................................................... 46 Functions of Bank Register ....................................................................................................... 46
WINDOW REGISTER (WR) .................................................................................................................... 45
BANK REGISTER (BANK) ..................................................................................................................... 46
INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP) ...................................................................................................................... 47 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 Index Register (IX) .................................................................................................................... 47 Data Memory Row Address Pointer (Memory Pointer: MP) .................................................... 47 IXE = 0 and MPE = 0 (No Data Memory Modification) ........................................................... 49 IXE = 0 and MPE = 1 (Diagonal Indirect Data Transfer) ......................................................... 51 IXE = 1 and MPE = 0 (Index Modification) ............................................................................... 53 General Register Pointer Configuration ................................................................................... 57 Functions of the General Register Pointer ............................................................................... 58 Program Status Word Configuration ......................................................................................... 59 Functions of the Program Status Word .................................................................................... 60 Index Enable Flag (IXE) ............................................................................................................ 61 Zero Flag (Z) and Compare Flag (CMP) .................................................................................. 61 Carry Flag (CY) ......................................................................................................................... 61 Binary-Coded Decimal Flag (BCD) ........................................................................................... 62 Notes Concerning Use of Arithmetic Operations ..................................................................... 62 Reserved Words for the System Register ................................................................................ 63 Handling of System Register Addresses Fixed at 0 ................................................................ 65
7.6
GENERAL REGISTER POINTER (RP) .................................................................................................. 57 7.6.1 7.6.2
7.7
PROGRAM STATUS WORD (PSWORD) ............................................................................................... 59 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7
7.8
NOTES CONCERNING USE OF THE SYSTEM REGISTER ............................................................... 63 7.8.1 7.8.2
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CHAPTER 8 GENERAL REGISTER (GR) ........................................................................................... 67
8.1 8.2 GENERAL REGISTER CONFIGURATION ............................................................................................ 67 FUNCTIONS OF THE GENERAL REGISTER ....................................................................................... 67
CHAPTER 9 REGISTER FILE (RF) ...................................................................................................... 69
9.1 REGISTER FILE CONFIGURATION ...................................................................................................... 69 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.3 9.3 9.4 Configuration of the Register File ............................................................................................. 69 Relationship between the Register File and Data Memory ..................................................... 69 Functions of the Register File ................................................................................................... 70 Functions of Control Register ................................................................................................... 70 Register File Manipulation Instructions .................................................................................... 71
FUNCTIONS OF THE REGISTER FILE ................................................................................................. 70
CONTROL REGISTER ............................................................................................................................ 72 NOTES CONCERNING USE OF THE REGISTER FILE....................................................................... 73 9.4.1 9.4.2 Notes Concerning Operation of the Control Register (Read-Only and Unused Registers) ... 73 Register File Symbol Definitions and Reserved Words ........................................................... 73
CHAPTER 10
DATA BUFFER (DBF) ................................................................................................... 77
10.1 DATA BUFFER CONFIGURATION ........................................................................................................ 77 10.2 FUNCTIONS OF THE DATA BUFFER ................................................................................................... 78 10.2.1 10.2.2 10.2.3 Data Buffer and Peripheral Hardware ...................................................................................... 79 Data Transfer with Peripheral Hardware .................................................................................. 80 Table Reference ......................................................................................................................... 81
CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU) ....................................................................... 83
11.1 ALU BLOCK CONFIGURATION ............................................................................................................ 83 11.2 FUNCTIONS OF THE ALU BLOCK ....................................................................................................... 83 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 Functions of the ALU ................................................................................................................. 83 Functions of Temporary Registers A and B .............................................................................. 88 Functions of the Status Flip-flop ............................................................................................... 88 Operations in 4-Bit Binary ......................................................................................................... 89 Operations in BCD ..................................................................................................................... 89 Operations in the ALU Block ..................................................................................................... 90 Addition and Subtraction When CMP = 0 and BCD = 0 .......................................................... 91 Addition and Subtraction When CMP = 1 and BCD = 0 .......................................................... 91 Addition and Subtraction When CMP = 0 and BCD = 1 .......................................................... 92 Addition and Subtraction When CMP = 1 and BCD = 1 .......................................................... 92 Notes Concerning Use of Arithmetic Operations ..................................................................... 92
11.3 ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD) ....... 91
11.4 LOGICAL OPERATIONS ........................................................................................................................ 93 11.5 BIT JUDGEMENTS ................................................................................................................................. 94 11.5.1 11.5.2 TRUE (1) Bit Judgement ........................................................................................................... 94 FALSE (0) Bit Judgement ......................................................................................................... 95
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11.6 COMPARISON JUDGEMENTS .............................................................................................................. 96 11.6.1 11.6.2 11.6.3 11.6.4 11.7.1 11.7.2 "Equal to" Judgement ................................................................................................................ 96 "Not Equal to" Judgement ......................................................................................................... 97 "Greater Than or Equal to" Judgement .................................................................................... 97 "Less Than" Judgement ............................................................................................................ 98 Rotation to the Right ................................................................................................................. 99 Rotation to the Left .................................................................................................................. 100
11.7 ROTATIONS ............................................................................................................................................. 99
CHAPTER 12 PORTS ......................................................................................................................... 101
12.1 PORT 0A (P0A0, P0A1, P0A2, P0A3) .................................................................................................... 101 12.2 PORT 0B (P0B0, P0B1, P0B2, P0B3) .................................................................................................... 102 12.3 PORT 0C (P0C0/ADC0, P0C1/ADC1, P0C2/ADC2, P0C3/ADC3) .......................................................... 103 12.4 PORT 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TM0OUT) ................................................................ 104 12.5 PORT 1A (P1A0, P1A1, P1A2, P1A3) .................................................................................................... 105 12.6 PORT 1B (P1B0) .................................................................................................................................... 105 12.7 PORT CONTROL REGISTER ............................................................................................................... 106 12.7.1 12.7.2 12.7.3 Input/Output Switching by Group I/O ...................................................................................... 106 Input/Output Switching by Bit I/O ........................................................................................... 107 Specifying Pull-Up Resistor Incorporation Using Software ................................................... 109
CHAPTER 13 PERIPHERAL HARDWARE ......................................................................................... 111
13.1 8-BIT TIMERS/COUNTERS (TM0 and TM1) ........................................................................................ 111 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.1.6 13.1.7 13.1.8 13.2.1 13.2.2 13.2.3 13.2.4 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.4.1 13.4.2 13.4.3 13.4.4 8-Bit Timers/Counters Configuration ....................................................................................... 111 Operation of 8-Bit Timers/Counters ........................................................................................ 115 Selecting Count Pulse ............................................................................................................. 115 Setting Count Value to Modulo Register ................................................................................ 116 Reading Value of Count Register ........................................................................................... 117 Setting of Interval Time ........................................................................................................... 118 Error of Interval Time ............................................................................................................... 119 Timer 0 Output ......................................................................................................................... 121 Basic Interval Timer Configuration .......................................................................................... 122 Registers Controlling Basic Interval Timer ............................................................................. 123 Operation of Basic Interval Timer ........................................................................................... 124 Watchdog Timer Function ....................................................................................................... 125 A/D Converter Configuration ................................................................................................... 128 Functions of A/D Converter ..................................................................................................... 129 Setting Values in the 8-bit Data Register (ADCR) ................................................................. 132 Reading Values from the 8-bit Data Register (ADCR) .......................................................... 133 A/D Converter Operation ......................................................................................................... 134 Functions of the Serial Interface ............................................................................................. 141 3-wire Serial Interface Operation Modes ................................................................................ 143 Setting Values in the Shift Register ........................................................................................ 147 Reading Values from the Shift Register ................................................................................. 148
13.2 BASIC INTERVAL TIMER (BTM) ......................................................................................................... 122
13.3 A/D CONVERTER ................................................................................................................................. 128
13.4 SERIAL INTERFACE (SIO) .................................................................................................................. 141
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CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................ 149
14.1 INTERRUPT SOURCE TYPES AND VECTOR ADDRESSES ............................................................ 150 14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT ....................................... 151 14.3 INTERRUPT SEQUENCE ..................................................................................................................... 158 14.3.1 14.3.2 14.3.3 Receiving an Interrupt ............................................................................................................. 158 Return from the Interrupt Routine ........................................................................................... 159 Interrupt Accepting Timing ...................................................................................................... 160
14.4 MULTI-INTERRUPT ............................................................................................................................... 163 14.5 PROGRAM EXAMPLE OF INTERRUPT ............................................................................................. 164
CHAPTER 15 AC ZERO CROSS DETECTION .................................................................................. 167 CHAPTER 16 STANDBY FUNCTION .................................................................................................. 169
16.1 OVERVIEW OF THE STANDBY FUNCTION ....................................................................................... 169 16.2 HALT MODE .......................................................................................................................................... 170 16.2.1 16.2.2 16.2.3 16.3.1 16.3.2 16.3.3 Setting HALT Mode ................................................................................................................. 170 Start Address after HALT Mode Is Released ......................................................................... 170 HALT Mode Setting Conditions ............................................................................................... 172 Setting of STOP Mode ............................................................................................................ 174 Start Address after STOP Mode Is Released ........................................................................ 174 STOP Mode Setting Conditions .............................................................................................. 176
16.3 STOP MODE .......................................................................................................................................... 174
CHAPTER 17 RESET ........................................................................................................................... 179
17.1 RESET FUNCTION ................................................................................................................................ 180 17.2 RESETTING ........................................................................................................................................... 181 17.3 POWER-ON/POWER-DOWN RESET FUNCTION .............................................................................. 182 17.3.1 17.3.2 17.3.3 17.3.4 Conditions Required to Enable the Power-On Reset Function ............................................. 182 Power-On Reset Function and Operation .............................................................................. 183 Condition Required for Use of the Power-Down Reset Function .......................................... 185 Power-Down Reset Function and Operation .......................................................................... 185
CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING.................................................................... 189
18.1 DIFFERENCES BETWEEN MASK ROM VERSION AND ONE-TIME PROM MODEL..................... 189 18.2 OPERATION MODE WHEN PROGRAM MEMORY IS WRITTEN/VERIFIED ................................... 190 18.3 WRITING PROCEDURE OF PROGRAM MEMORY ........................................................................... 191 18.4 READING PROCEDURE OF PROGRAM MEMORY .......................................................................... 192
CHAPTER 19 INSTRUCTION SET ...................................................................................................... 193
19.1 OVERVIEW OF THE INSTRUCTION SET ........................................................................................... 193 19.2 LEGEND ................................................................................................................................................. 194 19.3 LIST OF THE INSTRUCTION SET ....................................................................................................... 195 19.4 ASSEMBLER (AS17K) EMBEDDED MACRO INSTRUCTIONS ........................................................ 197
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19.5 INSTRUCTIONS .................................................................................................................................... 198 19.5.1 19.5.2 19.5.3 19.5.4 19.5.5 19.5.6 19.5.7 19.5.8 19.5.9 Addition Instructions ................................................................................................................ 198 Subtraction Instructions ........................................................................................................... 209 Logical Operation Instructions ................................................................................................ 216 Judgment Instructions ............................................................................................................. 221 Comparison Instructions .......................................................................................................... 223 Rotation Instructions ................................................................................................................ 226 Transfer Instructions ................................................................................................................ 227 Branch Instructions .................................................................................................................. 243 Subroutine Instructions ............................................................................................................ 246
19.5.10 Interrupt Instructions ................................................................................................................ 251 19.5.11 Other Instructions .................................................................................................................... 253
CHAPTER 20 ASSEMBLER RESERVED WORDS ............................................................................ 255
20.1 MASK OPTION DIRECTIVE ................................................................................................................. 255 20.1.1 Specifying Mask Option .......................................................................................................... 255 20.2 RESERVED SYMBOLS ......................................................................................................................... 257
APPENDIX A DEVELOPMENT OF PD171xx SUBSERIES ............................................................. 261 APPENDIX B COMPARISON OF FUNCTIONS BETWEEN PD17135A, 17137A, AND PD17145 SUBSERIES ................................................................................................ 263 APPENDIX C DEVELOPMENT TOOLS .............................................................................................. 265 APPENDIX D NOTES ON CONFIGURATION OF SYSTEM CLOCK OSCILLATION CIRCUIT ...... 267 APPENDIX E INSTRUCTION LIST ...................................................................................................... 269
E.1 E.2 INSTRUCTION LIST (by function) ...................................................................................................... 269 IINSTRUCTION LIST (alphabetical order) ......................................................................................... 270
APPENDIX F ORDERING MASK ROM ............................................................................................... 271
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LIST OF FIGURES (1/3)
Figure No. 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 8-1
Title
Page
Program Counter ...................................................................................................................................... 17 Value of the Program Counter after Instruction Execution .................................................................... 18 Value in the Program Counter after Reset ............................................................................................. 18 Value in the Program Counter during Execution of a BR addr Instruction ........................................... 18 Value in the Program Counter during Execution of an Indirect Branch Instruction .............................. 19 Value in the Program Counter during Execution of a CALL addr .......................................................... 19 Value in the Program Counter during Execution of an Indirect Subroutine Call .................................. 20 Value in the Program Counter during Execution of a Return Instruction .............................................. 20 Program Memory Map for the PD17134A Subseries ........................................................................... 23 CALL addr Instruction .............................................................................................................................. 26 Table Reference (MOVT DBF, @AR) ...................................................................................................... 27 Data Memory Configuration ..................................................................................................................... 31 System Register Configuration ................................................................................................................ 32 Data Buffer Configuration ........................................................................................................................ 32 General Register (GR) Configuration ...................................................................................................... 33 Port Register Configuration ..................................................................................................................... 33 Stack Configuration .................................................................................................................................. 35 Allocation of System Register in Data Memory ...................................................................................... 41 System Register Configuration ................................................................................................................ 42 Address Register Configuration .............................................................................................................. 43 Address Register Used as a Peripheral Circuit ...................................................................................... 44 Window Register Configuration ............................................................................................................... 45 Example of Window Register Operation ................................................................................................. 45 Bank Register Configuration ................................................................................................................... 46 Index Register Configuration ................................................................................................................... 47 Modification of Data Memory Address by Index Register and Memory Pointer ................................... 48 Operation Example When IXE = 0 and MPE = 0 ................................................................................... 50 Operation Example When IXE = 0 and MPE = 1 ................................................................................... 52 Operation Example When IXE = 1 and MPE = 0 ................................................................................... 54 Operation Example When IXE = 1 and MPE = 0 ................................................................................... 55 Operation Example When IXE = 1 and MPE = 0 (Array Processing) ................................................... 56 General Register Pointer Configuration .................................................................................................. 57 General Register Configuration ............................................................................................................... 58 Program Status Word Configuration ....................................................................................................... 59 Outline of Functions of the Program Status Word ................................................................................. 60 General Register Configuration ............................................................................................................... 68
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LIST OF FIGURES (2/3)
Figure No. 9-1 9-2 9-3 9-4 10-1 10-2 10-3 11-1 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27
Title
Page
Register File Configuration ...................................................................................................................... 69 Relationship Between the Register File and Data Memory ................................................................... 70 Accessing the Register File Using the PEEK and POKE Instructions .................................................. 72 Control Register Configuration ................................................................................................................ 75 Allocation of the Data Buffer ................................................................................................................... 77 Data Buffer Configuration ........................................................................................................................ 77 Relationship Between the Data Buffer and Peripheral Hardware ......................................................... 78 ALU Configuration .................................................................................................................................... 84 Input/Output Switching by Group I/O .................................................................................................... 106 Port Control Register of Bit I/O ............................................................................................................. 107 Specifying Pull-Up Resistor Incorporation Using Software .................................................................. 109 Configuration of the 8-Bit Timer Counters ............................................................................................ 112 Timer 0 Mode Register .......................................................................................................................... 113 Timer 1 Mode Register .......................................................................................................................... 114 Setting Count Value to Modulo Register ............................................................................................... 116 Reading Count Value of Count Register ............................................................................................... 117 Error When Count Register Is Cleared to 0 During Counting ............................................................. 119 Error When Counting Is Started from Count Stop Status .................................................................... 120 Timer 0 Output Setting Register ............................................................................................................ 121 Basic Interval Timer Configuration ........................................................................................................ 122 BTM Mode Register ............................................................................................................................... 123 Watchdog Timer Mode Register ............................................................................................................ 124 Timing Chart of Watchdog Timer (with WDTRES Flag Used) ............................................................. 126 Block Diagram of the A/D Converter ..................................................................................................... 128 A/D Converter Control Register ............................................................................................................ 130 Setting a Value in the 8-Bit Data Register (ADCR) .............................................................................. 132 Reading Values from the 8-bit Data Register (ADCR) ......................................................................... 133 Relationship between the Analog Input Voltage and Digital Conversion Result ................................ 134 Using the Successive Mode for the A/D Converter .............................................................................. 136 A/D Conversion Timing in the Continuous Mode ................................................................................. 137 Using the Single Mode for the A/D Converter ...................................................................................... 139 Single Mode Operation (Comparison) Timing ...................................................................................... 140 Block Diagram of the Serial Interface ................................................................................................... 142 Timing of 8-Bit Transmission and Reception Mode (Simultaneous Transmission and Reception) .. 143 Timing of the Clock Synchronization 8-Bit Reception Mode (SO Pin Output High Impedance) ........ 144 Serial Interface Control Register ........................................................................................................... 145 Setting a Value in the Shift Register ..................................................................................................... 147 Reading a Value from the Shift Register .............................................................................................. 148
- viii -
LIST OF FIGURES (3/3)
Figure No. 14-1 14-2 14-3 14-4 14-5 15-1 15-2 16-1 16-2 17-1 17-2 17-3 17-4 17-5 18-1 18-2 D-1 D-2
Title
Page
Interrupt Control Register ...................................................................................................................... 152 Interrupt Processing Procedure ............................................................................................................ 158 Return from Interrupt Processing .......................................................................................................... 159 Interrupt Accepting Timing (When INTE = 1, IPxxx = 1) ..................................................................... 160 Example of Multi-interrupt ..................................................................................................................... 163 Block Diagram for the AC Zero Cross Detector ................................................................................... 167 Zero Cross Detection Signal ................................................................................................................. 168 Releasing HALT Mode ........................................................................................................................... 171 Releasing STOP Mode .......................................................................................................................... 175 Reset Block Configuration ..................................................................................................................... 181 Reset Operation ..................................................................................................................................... 181 Example of the Power-On Reset Operation ......................................................................................... 184 Example of the Power-Down Reset Operation ..................................................................................... 186 Example of Reset Operation during the Period from Power-Down Reset to Power Recovery ......... 187 Procedure of Program Memory Writing ................................................................................................ 191 Procedure of Program Memory Reading .............................................................................................. 192 External Circuit of System Clock Oscillation Circuit ............................................................................. 267 Example of Incorrect Oscillation Circuits .............................................................................................. 268
- ix -
LIST OF TABLES (1/2)
Table No. 2-1 4-1 4-2 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 14-1 14-2 16-1 16-2 16-3 16-4 16-5
Title
Page
Processing of Unused Pins ..................................................................................................................... 14 Program Memory Configuration .............................................................................................................. 23 Vector Address for the PD17134A Subseries ...................................................................................... 24 Operation of Stack Pointer ...................................................................................................................... 37 Operation of the Instructions CALL, RET, and RETSK .......................................................................... 38 Stack Operation during Table Reference ................................................................................................ 38 Operation during Interrupt Receipt and RETI Instruction ...................................................................... 39 Stack Operation during the PUSH and POP Instructions ...................................................................... 39 Specifying the Bank in Data Memory ...................................................................................................... 46 Instructions Subject to Address Modification .......................................................................................... 48 Zero Flag (Z) and Compare Flag (CMP) ................................................................................................ 61 Peripheral Hardware ................................................................................................................................ 79 List of ALU Instructions ............................................................................................................................ 86 Results of Arithmetic Operations Performed in 4-Bit Binary and BCD .................................................. 89 Types of Arithmetic Operations ............................................................................................................... 91 Logical Operations ................................................................................................................................... 93 Table of True Values for Logical Operations .......................................................................................... 93 Bit Judgement Instructions ...................................................................................................................... 94 Comparison Judgement Instructions ....................................................................................................... 96 Writing into and Reading from the Port Register (0.70H) .................................................................... 101 Writing into and Reading from the Port Register (0.71H) .................................................................... 102 Switching the Port and A/D Converter .................................................................................................. 103 Register File Contents and Pin Functions ............................................................................................ 104 Contents Read from the Port Register (0.73H) .................................................................................... 105 Writing into and Reading from the Port Register (1.70H) .................................................................... 105 Data Conversion Time for the A/D Converter ....................................................................................... 138 Serial Clock List ..................................................................................................................................... 141 Operating Mode of the Serial Interface ................................................................................................. 143 Interrupt Source Types .......................................................................................................................... 150 Interrupt Request Flag and Interrupt Enable Flag ................................................................................ 151 Status in Standby Mode ........................................................................................................................ 169 HALT Mode Release Condition ............................................................................................................. 170 Start Address after HALT Mode Is Released ........................................................................................ 170 STOP Mode Release Condition ............................................................................................................ 174 Start Address after STOP Mode Is Released ....................................................................................... 174
-x-
LIST OF TABLES (2/2)
Table No. 17-1 18-1 18-2 18-3 20-1
Title
Page
Hardware Status at Reset ..................................................................................................................... 180 Pins Used for Writing/Verifying Program Memory ................................................................................ 189 Differences Between Mask ROM Version and One-Time PROM Version .......................................... 190 Setting Operation Modes ....................................................................................................................... 190 Mask Option Definition Directive ........................................................................................................... 256
- xi -
[MEMO]
- xii -
CHAPTER 1 GENERAL DESCRIPTION
1
The PD17134A subseries is a 4-bit single-chip microcontroller employing the 17K architecture and containing an 8-bit A/D converter (4 channels), a timer (3 channels), an AC zero cross detector, a power-on reset circuit, and a serial interface. The PD17P136A and 17P137A are the one-time PROM version of the PD17136A and 17137A, respectively, and are suitable for program evaluation at system development and for small-scale production. The following are features of the PD17134A subseries.
* * *
17K architecture: general-purpose register mode, instruction length: fixed to 16 bits Instruction execution time: 2 s (fX = 8 MHz, ceramic oscillation) 8 s (fCC = 2 MHz, RC oscillation) Program memory: PD17134A : 2K bytes (1024 x 16 bits) : 2K bytes (1024 x 16 bits) : 4K bytes (2048 x 16 bits) : 4K bytes (2048 x 16 bits)
PD17135A PD17136A PD17137A
PD17P136A : 4K bytes (2048 x 16 bits, one-time PROM) PD17P137A : 4K bytes (2048 x 16 bits, one-time PROM)
* * * * *
Data memory (RAM): 112 x 4 bits A/D converter: 4 channels (8-bit resolution, successive approximation type) Timer: 3 channels (8-bit timer/counter x 2 channels, basic interval timerNote) Serial interface: 1 channel (clocked 3-wire mode) Supply voltage: VDD = 4.5 to 5.5 V (fX = 400 kHz to 8 MHz) VDD = 2.7 to 5.5 V (fX = 400 kHz to 4 MHz) VDD = 2.7 to 5.5 V (fCC = 400 kHz to 2 MHz) for PD17134A and 17136A Note An internal reset signal can be generated by using the basic interval timer (watchdog timer function).
These features of the PD17134A subseries are suitable for use as a controller or a slave device in the following application fields;
* * * * * *
Electronic thermos bottle Rice cooker Audio equipment Battery charger Printer Plain Paper Copier
1
CHAPTER 1 GENERAL DESCRIPTION
1.1 FUNCTION LIST
Item ROM configuration ROM capacity RAM capacity Stack Number of I/O port 22
PD17134A
Mask ROM
PD17135A
PD17136A
PD17137A
PD17P136A
PD17P137A
One-time PROM 4KB (2048 ! 16 bits)
2KB (1024 ! 16 bits) 112 ! 4 bits
Address stack x 5, interrupt stack x 3 * I/O : 20 * Input only :1 * Sensor inputNote : 1
A/D converter Timer
8-bit resolution x 4 channels (shared with port pin), absolute precision 1.5 LSB or less 3 channels * 8-bit timer counter : 2 channels (16-bit timer 1 channel applicable) * 7-bit basic interval timer : 1 channel (watchdog timer applicable)
Serial interface AC zero cross detection function Interrupt
1 channel (3 wires) Provided (can be used in application circuit at VDD = 5 V 10%) * Nesting by hardware (up to 3 levels) Rising edge detection * External interrupts (INT) : 1 Falling edge detection Both rising and falling edges detection * Timer 0 (TM0) * Timer 1 (TM1) * Internal interrupts :1 * Basic interval timer (BTM) * Serial interface (SIO)
Selectable
System clock
RC oscillation 8 s at fX = 2 MHz HALT, STOP
Ceramic oscillation 2 s at fX = 8 MHz
RC oscillation 8 s at fX = 2 MHz
Ceramic oscillation 2 s at fX = 8 MHz
RC oscillation 8 s at fX = 2 MHz
Ceramic oscillation 2 s at fX = 8 MHz
Instruction execution time Standby Power-on/ power-down reset Supply voltage Package
Available (effective only for application circuit with VDD = 5 V 10 %, 400 kHz to 4 MHz) VDD = 2.7 to 5.5 V (5 V 10 % when using A/D converter) 28-pin plastic shrink DIP, 28-pin plastic SOP
Note
The INT pin can be used as an input pin (sense input) when the external interrupt function is not used. The sense input function is to read the status of the pin by using the INT flag of a control register, instead of a port register.
Caution The PROM model is highly compatible with the mask ROM model in terms of functions but its internal ROM circuit and electrical characteristics are partially different from those of the mask ROM model. To replace the PROM model with the mask ROM model, thoroughly evaluate the application by using a sample of the mask ROM model.
2
CHAPTER 1 GENERAL DESCRIPTION
1.2 ORDERING INFORMATION Part number Package 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM One-time PROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM One-time PROM
PD17134ACT-xxx PD17135ACT-xxx PD17136ACT-xxx PD17137ACT-xxx PD17P136ACT PD17P137ACT PD17134AGT-xxx PD17135AGT-xxx PD17136AGT-xxx PD17137AGT-xxx PD17P136AGT PD17P137AGT
Remark xxx: ROM code number
3
CHAPTER 1 GENERAL DESCRIPTION
1.3 BLOCK DIAGRAM
VDD
POWER-ON/ POWER-DOWN RESET
Clock divider fX/2N
System clock generator CPU CLOCK CLK STOP
XIN (CLK)Note2 XOUT
P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0/ADC0 P0C1/ADC1 P0C2/ADC2 P0C3/ADC3
RF P0A (CMOS) RAM 112 x 4 bits SYSTEM REG. IRQBTM P0B (CMOS) Basic interval timer fX/2N Interrupt controller
IRQTM0 IRQTM1 IRQBTM IRQSIO
AC ZEROCROSS detector
INT
IRQTM1 ALU P0C (CMOS) Timer 1 fX/2N
IRQTM0
A/D Converter P0D0/SCK P0D1/SO P0D2/SI P0D3/TM0OUT
Timer 0
fX/2N
P0D (N-ch) Serial Interface TM0 IRQSIO
ROM/ One-Time PROM
Note1
P1A (N-ch) Instruction decoder P1B
P1A0 P1A1 P1A2 P1A3
P1B0 (VPP)
Program counter RESET StackNote2
GND
Remarks 1.
The terms CMOS and N-ch in square brackets indicate the output form of the port. CMOS : CMOS push-pull output N-ch : N-channel open-drain output (Each pin can contain pull-up resistor bit-wise as specified using a mask option.)
2.
The devices in parentheses are effective only in the case of program memory write/verify mode of the PD17P136A and PD17P137A.
Notes 1.
The ROM (or PROM) capacity of each product is as follows: 1024 x 16 bits : PD17134A, 17135A 2048 x 16 bits : PD17136A, 17137A, 17P136A, 17P137A
2.
The stack capacity of each product is as follows: 5 x 10 bits 5 x 11 bits : PD17134A, 17135A : PD17136A, 17137A
4
CHAPTER 1 GENERAL DESCRIPTION
1.4 PIN CONFIGURATION (TOP VIEW) (1) Normal operating mode 28-pin plastic shrink DIP (400 mil)
PD17134ACT-xxx, PD17135ACT-xxx, PD17136ACT-xxx, PD17137ACT-xxx PD17P136ACT-xxx, PD17P137ACT-xxx
28-pin plastic SOP (375 mil)
PD17134AGT-xxx, PD17135AGT-xxx, PD17136AGT-xxx, PD17137AGT-xxx PD17P136AGT-xxx, PD17P137AGT-xxx
VADC P0C3/ADC3 P0C2/ADC2 P0C1/ADC1 P0C0/ADC0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD XIN (OSC1) XOUT (OSC0) P0D0/SCK P0D1/SO P0D2/SI P0D3/TM0OUT P1A0 P1A1 P1A2 P1A3 P1B0 RESET INT
ADC0 to ADC3 GND INT OSC0, OSC1 P0A0 to P0A3 P0B0 to P0B3 P0C0 to P0C3 P0D0 to P0D3 P1A0 to P1A3
: Analog input for the A/D converter : Ground : External interrupt input : System clock oscillation : Port 0A : Port 0B : Port 0C : Port 0D : Port 1A
P1B0 RESET SCK SI SO TM0OUT VADC VDD XIN, XOUT
: Port 1B : Reset input : Serial clock input/output : Serial data input : Serial data output : Timer 0 carry output : Analog power supply : Power supply : System clock oscillation
5
CHAPTER 1 GENERAL DESCRIPTION
(2) Program memory write/verify mode 28-pin plastic shrink DIP (400 mil)
PD17P136ACT, 17P137ACT
28-pin plastic SOP (375 mil)
PD17P136AGT, 17P137AGT
(VDD) MD3 MD2 MD1 MD0 D7 D6 D5 D4 D3 D2 D1 D0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22
VDD CLK (Open)
(L) 21 20 19 18 17 16 15 VPP RESET (L)
Caution ( ) represents processing of the pins which are not used in program memory write/verify mode. L : Connect to GND via pull-down resistor one by one. RESET pin is also used for system reset input before setting program memory write/verify mode. Therefore, RESET pin should be set to the same electric potential as VDD 10 s or later than that of VDD pin (For details, refer to CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING). Open VDD : Do not connect anything. : Connect to VDD directly. RESET : Set the same electric potential as VDD in program memory write/verify mode.
6
CHAPTER 1 GENERAL DESCRIPTION
CLK D0-D7 GND RESET VDD VPP
: Clock input for address updating : Data input/output : Ground : Reset input : Power supply : Program voltage application
MD0-MD3 : Operation mode select
7
[MEMO]
8
CHAPTER 2 PIN FUNCTIONS
2.1 PIN FUNCTIONS
Pin No. 1 2 | 5 Pin name VADC P0C3/ADC3/MD3 | P0C0/ADC0/MD0 Note1
Note1
Function Supplies power and reference voltage for the A/D converter Constitute port 0C, serve as analog input pins of A/D converter, or select operating mode when program memory is written or verified. P0C3 to P0C0 * 4-bit input/output port * Input/output setting in 1-bit unit ADC3 to ADC0 * Analog input for the A/D converter MD3 to MD0 * Available for the PD17P136A and PD17P137A only * Selects operating mode at program memory writing/ verification
Output -- CMOS push-pull
At reset -- Input (P0C)
* * *
6 | 9
P0B3/D7 Note1 | P0B0/D4 Note1
Used as port 0B, or data input/output pins in program memory write/verify mode. P0B3 to P0B0 * 4-bit input/output port * Input/output setting in 4-bit unit * Software-selectable pull-up resistor D7 to D4 * Available for the PD17P136A and PD17P137A only * 8-bit data input/output at program memory writing/ verification
CMOS push-pull
Input (P0B)
*
*
10 | 13
P0A3/D3 Note1 | P0A0/D0 Note1
Used as port 0A, or data input/output pin in program memory write/verify mode. P0A3 to P0A0 * 4-bit input/output port * Input/output setting in 4-bit unit * Software-selectable pull-up resistor D3 to D0 * Available for the PD17P136A and PD17P137A only * 8-bit data input/output at program memory writing/ verification
CMOS push-pull
Input (P0A)
*
*
14 15 16
GND INT RESET
Ground External interrupt request input or sensor signal input System reset input pin A pull-up resistor can be internally connected by mask option Note2
-- -- --
-- Input Input
Notes 1. 2.
The MD0-MD3 and D0-D7 pins are valid with the PD17P136A and 17P137A only. The PD17P136A and 17P137A do not have a pull-up resistor connected by mask option.
9
CHAPTER 2 PIN FUNCTIONS
Pin No. 17
Pin name P1B0/VPP
Note1
Function Used as port 1B, or programming voltage supply pin in program memory write/verify mode. P1B0 * 1-bit input port * A pull-up resistor can be internally connected by mask option Note2 VPP * Available for the PD17P136A and PD17P137A only * Applies programming voltage (+12.5 V) at program memory writing/verification
Output Input
At reset Input
*
*
18 | 21
P1A3 | P1A0
Port * * *
1A 4-bit input/output port Input/output setting in 4-bit unit A pull-up resistor can be internally connected by mask option Note2
N-ch open drain
Input
22
P0D3/TM0OUT
Used as port 0D, or timer 0 carry output, serial data input, serial data output, and serial clock input/output pins A pull-up resistor can be internally connected by mask option Note2
N-ch open drain
Input
* *
23 24 25 P0D2/SI P0D1/SO P0D0/SCK
* * * * *
P0D3 to P0D0 * 4-bit input/output port * Input/output setting in 1 bit unit TM0OUT * Timer 0 carry output SI * Serial data input SO * Serial data output SCK * Serial clock input/output -- --
26 27
XOUT XIN/CLK Note3
In the case of the PD17135A/17137A/17P137A XIN, XOUT * Connected to a resonator for system clock oscillation * The ceramic resonator is connected. CLK * Available for the PD17P137A only * Clock input pin for address updating at program memory writing/verification In the case of the PD17134A/17136A/17P136A OSC0, OSC1 * Connected to a resonator for system clock oscillation * Resistor is connected between OSC0 and OSC1. CLK * Available for the PD17P136A only * Clock input pin for address updating at program memory writing/verification
26 27
OSC0 OSC1/CLK Note3
* *
28
VDD
Power supply In the program memory write/verify mode of the PD17P136A/17P137A, +6 V is applied.
--
--
Notes 1. 2. 3.
The VPP pin is valid only with the PD17P136A and 17P137A. The PD17P136A and 17P137A do not have a pull-up resistor connected by mask option. The CLK pin is valid only with the PD17P136A and 17P137A.
10
CHAPTER 2 PIN FUNCTIONS
2.2 PIN INPUT/OUTPUT CIRCUIT
1
Below are simplified diagrams of the input/output circuits for each pin.
2
(1) P0A0-P0A3, P0B0-P0B3
VDD P-ch Output latch Pull-up flag VDD
3 4 5
P-ch
Data
6
Output disable N-ch
7 8 9
Selector
10 11
VDD
Input buffer
(2) P0C0/ADC0 - P0C3/ADC3
12 13
Data
Output latch
P-ch
14 15
Output disable Input disable
N-ch
16 17 18 19 20
Input buffer A/D converter
Selector
11
CHAPTER 2 PIN FUNCTIONS
(3) P0D0-P0D3, P1A0-P1A3
VDD
Data
Output latch
Mask optionNote
Output disable
N-ch
Selector
Input buffer
Note The PD17P136A and 17P137A do not have a pull-up resistor as mask option. (4) P1B0
VDD
Mask optionNote
Input buffer
Note The PD17P136A and 17P137A do not have a pull-up resistor as mask option.
12
CHAPTER 2 PIN FUNCTIONS
(5) INT
1 2
Input buffer
3 4
(6) RESET
VDD
5 6 7
Mask optionNote
8 9
Input buffer
10
Note The PD17P136A and 17P137A do not have a pull-up resistor as mask option.
11 12 13 14 15 16 17 18 19 20
13
CHAPTER 2 PIN FUNCTIONS
2.3 PROCESSING OF UNUSED PINS The unused pins should be handled as follows: Table 2-1. Processing of Unused Pins
Pin Name Internal Port Input mode P0A, P0B P0C Connect pull-up resistor by software -- Open Connect each pin to VDD or GND via resistorNote 1 Directly connect to GND Recommended Processing External
P0D, P1A
Pull-up resistor not connected by mask option Pull-up resistor connected by mask option
Open
P1B0Note2
Pull-up resistor not connected by mask option --
Directly connect to GND
Output mode
P0A, P0B, P0C (CMOS port) P0D, P1A (N-ch opendrain ports)
Open
Outputs low level without pull-up resistor connected by mask option Outputs high level without pull-up resistor connected by mask option Pull-up resistor not connected by mask option Pull-up resistor connected by mask option Directly connect to VDD or GND
External interrupt (INT)
Open
RESETNote3 when only internal power-ON/powerdown reset function is used
Pull-up resistor not connected by mask option Pull-up resistor connected by mask option --
Directly connect to VDD
VADC
Directly connect to VDD
Notes 1.
When connecting an external pull-up resistor (to VDD via resistor) or pull-down resistor (to GND via resistor), make sure that the driving voltage and current consumption of the port are not exceeded. When connecting a pull-up or pull-down resistor with a high resistance to a port pin, make sure that noise is not superimposed on the pin. Generally, the resistance of the pull-up or pull-down resistor is about several k, though it varies depending on the application circuit.
2. 3.
Because the P1B0 pin is multiplexed with a test mode setting function, do not connect a pull-up resistor to this pin using the mask option. Directly connect it to GND. In an application circuit where high reliability is required, be sure to input the RESET signal from an external source. Because the RESET pin is multiplexed with a mode setting function, directly connect it to VDD if not use.
Caution It is recommended that the I/O mode, pull-up of resistors by software, and output levels of pins be fixed by repeatedly setting in each loop of the program. Remark The PD17P136A and 17P137A do not have a pull-up resistor as mask option.
14
CHAPTER 2 PIN FUNCTIONS
2.4 NOTES ON USING RESET PIN AND P1B0 PIN
1
The RESET and P1B0 pins have a function for setting a test mode in which the internal operations of the PD17134A subseries are tested (for IC test), in addition to the functions described in 2.1 PIN FUNCTIONS. When a voltage exceeding VDD is applied to either of these pins, the test mode is set. This means that, even during the normal operation, the test mode is set if a noise exceeding VDD is applied. As a result, the operation may not be performed normally. This is especially true if the wiring length of the RESET or P1B0 pin is too long in which case a noise may be superimposed on the wiring. Therefore, perform wiring so that noise may not be superimposed, by keeping the wiring length as short as possible. If noise is inevitable, take noise preventive measures by using an external component as illustrated below.
2 3 4 5 6 7
* Connect a diode with low VF between VDD and RESET/P1B0
VDD
* Connect a capacitor between VDD and RESET/P1B0
VDD
Diode with low VF RESET, P1B0
VDD
VDD
8 9
RESET, P1B0
10 11 12 13 14 15 16 17 18 19 20
15
[MEMO]
16
CHAPTER 3 PROGRAM COUNTER (PC)
The program counter is used to specify an address in program memory. 3.1 PROGRAM COUNTER CONFIGURATION Figure 3-1 shows the configuration of the program counter. The program counters of the PD17134A and PD17135A are 10-bit binary counters. The program counters of the PD17136A, PD17137A, PD17P136A, and PD17P137A are 11-bit binary counters. This program counter is incremented whenever an instruction is executed. Figure 3-1. Program Counter
MSB PC10 PC9 PC8 PC7 PC6 PC5 PC PC4 PC3 PC2 PC1
LSB PC0
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2 PROGRAM COUNTER OPERATION Normally, the program counter is automatically incremented each time a command is executed. The memory address at which the next instruction to be executed is stored is assigned to the program counter under the following conditions: At reset; when a branch, subroutine call, return, or table reference instruction is executed; or when an interrupt is received. 3.2.1 to 3.2.7 explain program counter operation during execution of each instruction.
17
CHAPTER 3 PROGRAM COUNTER (PC)
Figure 3-2. Value of the Program Counter after Instruction Execution
Program counter bit Instruction At reset BR addr
Program counter value PC10 PC9 0 0 PC8 0 PC7 0 PC6 0 PC5 0 PC4 0 PC3 0 PC2 0 PC1 0 PC0 0
Value set by the addr CALL addr BR @AR CALL @AR (MOVT DBF, @AR) RET RETSK RETI During interrupt Value in the address stack register location pointed to by the stack pointer (return address) Vector address for the interrupt
Value in the address register (AR)
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2.1 At Reset By setting the RESET pin to low, the program counter is set to 0000H. Figure 3-3. Value in the Program Counter after Reset
MSB 0 0 0 0 0 0 0 0 0 0 LSB 0
All bits are set to 0
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2.2 During Execution of the Branch Instruction (BR) There are two ways to specify branching using the branch instruction. One is to specify the branch address in the operand using the direct branch instruction (BR addr). The other is branch to the address specified by the address register using the indirect branch instruction (BR @AR). The address specified by a BR addr instruction is placed in the program counter. Figure 3-4. Value in the Program Counter during Execution of a BR addr Instruction
MSB PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 LSB PC0
Value specified in the direct branch instruction
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A.
18
CHAPTER 3 PROGRAM COUNTER (PC)
An indirect branch instruction causes the address in the address counter to be placed in the program counter. Figure 3-5. Value in the Program Counter during Execution of a BR @AR Instruction
MSB PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 LSB PC0
AR10
AR9
AR8
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2.3 During Execution of Subroutine Calls (CALL) There are two ways to specify branching using subroutine calls. One is to specify the branch address in the operand using the direct subroutine call (CALL addr). The other is branch to the address specified by the address register using the indirect subroutine call (CALL @AR). A CALL addr causes the value in the program counter to be saved in the stack and then the address specified in the operand to be placed in the program counter. CALL addr can specify 000H-03FFH in the PD17134A and 17135A, and 0000H-07FFH in the PD17136A, 17137A, 17P136A, and 17P137A. Figure 3-6. Value in the Program Counter during Execution of a CALL addr
MSB PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1
LSB PC0
Address specified in the addr
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. A CALL @AR causes the value in the program counter to be saved in the stack and then the value in the address register to be placed in the program counter.
19
CHAPTER 3 PROGRAM COUNTER (PC)
Figure 3-7. Value in the Program Counter during Execution of an Indirect Subroutine Call
Address stack register n (n = 0 to 4)
MSB PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1
LSB PC0
AR10
AR9
AR8
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2.4 During Execution of Return Instructions (RET, RETSK, RETI) During execution of a return instruction (RET, RETSK, RETI), the program counter is restored to the value saved in the address stack register. Figure 3-8. Value in the Program Counter during Execution of a Return Instruction
MSB PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1
LSB PC0
Address stack register n (n = 0 to 4)
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2.5 During Table Reference (MOVT) During execution of table reference (MOVT DBF, @AR), the value in the program counter is saved in the stack, the address register is set by the program counter, then the contents stored at that program memory location is read into the data buffer (DBF). After that, the program counter is restored to the value saved in the address stack register. One level of the address stack is temporarily used during execution of table reference. Be careful of the stack level.
20
CHAPTER 3 PROGRAM COUNTER (PC)
3.2.6 During Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT, SKF) When skip conditions are met and a skip instruction (SKE, SKGE, SKLT, SKNE, SKT, SKF) is executed, the instruction immediately following the skip instruction is treated as a no operation instruction (NOP). Therefore, whether skip conditions are met or not, the number of instructions executed and instruction execution time remain the same. 3.2.7 When an Interrupt Is Received When an interrupt is received, the value in the program counter is saved in the address stack. Next, the vector address for the interrupt received is placed in the program counter.
21
[MEMO]
22
CHAPTER 4 PROGRAM MEMORY (ROM)
The program organization of the PD17134A subseries is shown in Table 4-1. Table 4-1. Program Memory Configuration
Product name Program memory capacity 2K bytes (1024 x 16 bits) Program memory address 0000H-03FFH
PD17134A PD17135A PD17136A PD17137A PD17P136A PD17P137A
4K bytes (2048 x 16 bits)
0000H-07FFH
Program memory stores the program and the constant data table. The first area of the program memory is assigned to reset start and interrupt vector addresses. The program memory address is specified by the program counter. 4.1 PROGRAM MEMORY CONFIGURATION Figure 4-1 shows the program memory map. Branch instructions, subroutine calls, and table references can specify any address in program memory. Figure 4-1. Program Memory Map for the PD17134A Subseries
Address 0000H
16 bits Reset start address Subroutine entry address for the CALL addr instruction
0001H
Serial interface interrupt vector
0002H
Basic interval timer interrupt vector
Branch address for the BR addr instruction
0003H
Timer 1 interrupt vector Timer 0 interrupt vector Branch address for the BR @AR instruction
0004H
0005H
External (INT) interrupt vector
Subroutine entry address for the CALL @AR instruction
( mPD17134A/17135A) 03FFH Table reference address for the MOVT DBF, @AR instruction ( mPD17136A/17137A/17P136A/17P137A) 07FFH
23
CHAPTER 4 PROGRAM MEMORY (ROM)
4.2 PROGRAM MEMORY USAGE Program memory has the following two main functions: (1) Storage of the program (2) Storage of constant data The program is made up of the instructions which operate the CPU (Central Processing Unit). The CPU executes sequential processing according to the instructions stored in the program. In other words, the CPU reads each instruction in the order stored by the program in program memory and executes it. Since all instructions are 16-bit long words, each instruction is stored in a single address in program memory. Constant data, such as display patterns, are set beforehand. The MOVT is used for reading constant data in program memory to transfer data from program memory to the data buffer (DBF) in data memory. Reading the constant data in program memory is called table reference. Program memory is read-only (ROM: Read Only Memory) and therefore cannot be changed by any instructions. 4.2.1 Flow of the Program The program is usually stored in program memory starting from address 0000H and executed sequentially one address at a time. However, if for some reason a different kind of program is to be executed, it will be necessary to change the flow of the program. In this case, the branch instruction (BR instruction) is used. If the same program code is going to appear in a number of places, reproducing the code each time it needs to be used will decrease the efficiency of the program. In this case, the program should be stored in only one place in memory. Then, by using the CALL instruction, call the same program. Such a program is called a subroutine. As opposed to a subroutine, code used during normal operation is called the main routine. For cases completely unrelated to the flow of the program (in which a section of code is to be executed when a certain condition arises), the interrupt function is used. Whenever a condition arises that is unrelated to the flow of the program, the interrupt function can be used to branch the program to a prechosen memory location (called a vector address). Items (1) to (5) explain branching of the program using the interrupt function and instructions. (1) Vector address Table 4-2 shows the address to which the program is branched (vector address) when a reset or interrupt occurs. Table 4-2. Vector Address for the PD17134A Subseries
Vector address 0000H 0001H 0002H 0003H 0004H 0005H Reset Serial interface interrupt Basic interval timer interrupt Timer 1 interrupt Timer 0 interrupt External (INT) interrupt Cause of the interrupt
24
CHAPTER 4 PROGRAM MEMORY (ROM)
(2) Direct branch A direct branch (BR addr) instruction branches a value of operand (addr) as an address. (In the case of the
PD17134A and PD17135A, the most significant bit must be 0. If an address is specified outside of this range,
an error will occur in the assembler.) A BR addr instruction can be used to branch to any address in program memory. (3) Indirect branch When executing an indirect branch (BR @AR), the program branches to the address specified by the value stored in the address register (AR). A BR @AR can be used to branch to any address in program memory. Also see 7.2 ADDRESS REGISTER (AR). (4) Subroutine To branch execution to a subroutine, the subroutine call (CALL) instruction is used. The CALL instruction can be used in two ways: as a direct subroutine call instruction (CALL addr) that causes execution to branch using the value of the operand (addr) as an address, and as an indirect subroutine call instruction (CALL @AR) that causes execution to branch using the contents of an address register as an address. To return from a subroutine, the RET or RETSK instruction is used. By executing the RET or RETSK instruction, execution is returned to the program memory address next to the one at which the CALL instruction was executed. When the RETSK instruction is used, the first instruction after execution has returned from the subroutine is executed as a NOP instruction.
25
CHAPTER 4 PROGRAM MEMORY (ROM)
<1> Direct subroutine call When using a direct subroutine call (CALL addr), the 11-bit instruction operand is used to specify a program memory address of the branched subroutine. (In the case of the PD17134A and PD17135A, the most significant bit must be 0. If an address is specified outside of this range, an error will occur in the assembler.) Example Figure 4-2. CALL addr Instruction
Address 0000H
Program memory
CALL SUB1
SUB1;
RET
07FFHNote
Note The program memory of the PD17134A and PD17135A is address 0000H to 03FFH. <2> Indirect subroutine call When using an indirect subroutine call (CALL @AR), the value in the address register (AR) should be an address of the called subroutine. This instruction can be used to branch any address in program memory. Also see 7.2 ADDRESS REGISTER (AR).
26
CHAPTER 4 PROGRAM MEMORY (ROM)
4.2.2 Table Reference Table reference is used to reference constant data in program memory. The table reference instruction (MOVT DBF, @AR) is used to store the contents of the program memory address specified by the address register in the data buffer. Since each location in program memory contains 16 bits of information, the MOVT instruction causes 16 bits of data to be stored in the data buffer. The address register can be used to table reference any location in program memory. Caution Note that one level of the address stack is temporarily used when performing table reference. Be sure not to exceed the stack level that can be used. Also see 7.2 ADDRESS REGISTER (AR) and CHAPTER 10 DATA BUFFER (DBF). Remark Two instruction cycles are required to execute the table reference instruction, but this is an exception. Figure 4-3. Table Reference (MOVT DBF, @AR)
Data buffer Program memory DBF3 DBF2 DBF1 DBF0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0
16-bit data read
Address register AR3 AR2 AR1 AR0
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 0 0 0 0 0
Note
Constant data Table address specification
Note This bit is fixed to 0 in the case of the PD17134A and PD17135A.
27
CHAPTER 4 PROGRAM MEMORY (ROM)
(1) Constant data table Example 1 shows an example of code used to reference a constant data table. Example 1. Program to read data in a constant data table. OFFSET ROMREF: BANK0 ; Stores the start address of the constant data ; table in the AR register. MOV MOV MOV MOV MOV MOV ADD ADDC ADDC ADDC MOVT TABLE: DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW END 0001H 0002H 0004H 0008H 0010H 0020H 0040H 0080H 0100H 0200H 0400H 0800H 1000H 2000H 4000H 8000H ; When OFFSET = 0FH ; When OFFSET = 0H AR3, #.DL.TABLE SHR 12 AND 0FH AR2, #.DL.TABLE SHR 8 AND 0FH AR1, #.DL.TABLE SHR 4 AND 0FH AR0, #.DL.TABLE AND 0FH RPH, #0 RPL, #7 SHL 1 AR0, OFFSET AR1, #0 AR2, #0 AR3, #0 DBF, @AR ; Reads the constant data. ; Sets the register pointer to row address 7. ; ; Adds the offset address. MEM 0.00H ; Area to store the offset address.
28
CHAPTER 4 PROGRAM MEMORY (ROM)
(2) Branch address table Example 2 shows an example of code used to reference a branch address table. Example 2. Program to branch to the address of the branch address table. OFFSET ROMREF: BANK0 MOV MOV MOV MOV MOV MOV ADD ADDC MOVT PUT BR TABLE: DW DW DW DW DW DW DW DW DW DW END 0001H 0002H 0004H 0008H 0010H 0020H 0040H 0080H 0100H 0200H ; When OFFSET = 9H ; When OFFSET = 0H ; Stores the start address of the constant data ; table in the AR register. AR3, #.DL.TABLE SHR 12 AND 0FH AR2, #.DL.TABLE SHR 8 AND 0FH AR1, #.DL.TABLE SHR 4 AND 0FH AR0, #.DL.TABLE AND 0FH RPH, #0 RPL, #7 SHL 1 AR0, OFFSET AR1, #0 DBF, @AR AR, DBF @AR ; Reads the branch address ; AR Branch address ; Adds the offset address. ; Sets the register pointer to row address 7. MEM 0.00H ; Area to store the offset address.
29
[MEMO]
30
CHAPTER 5 DATA MEMORY (RAM)
Data memory stores data such as operation and control data. Data can be read from or written to data memory with an instruction during normal operation. 5.1 DATA MEMORY CONFIGURATION Figure 5-1 shows the configuration of data memory. Data memory is divided into two areas called banks: BANK0 and BANK1. An address is allocated to the data memory for each bank. An address consists of 4 bits of memory called "a nibble". The address of data memory consists of 7 bits. The high-order 3 bits are called "the row address", and the loworder 4 bits are called "the column address". For example, when the address of data memory is 1AH (0011010B), the row address is 1H (001B), and the column address is AH (1010B). 5.1.1 to 5.1.6 describe functions of data memory other than its use as address space. Figure 5-1. Data Memory Configuration
BANK0 0 0 1 Row address 2 3 4 5 6 7
P0A
(4 bits)
Column address 1 2 3 4 5 6 7 8 9 A B C D E F
DBF3 DBF2 DBF1 DBF0 Example Address 1AH of BANK0
P0B
P0C
P0D
(4 bits) (4 bits) (4 bits)
System register
BANK1 0 0 1 2 3 4 5 6 7
P1A P1B
(4 bits) (4 bits)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Unmounted
Fixed Fixed to 0 to 0
System register
Caution No hardware is assigned to addresses 00H through 6FH in BANK1. Do not use this area. If the contents of this area are read, the value is undefined. An instruction to write data to this area is invalid.
The same system register is allocated in each bank.
31
CHAPTER 5 DATA MEMORY (RAM)
5.1.1 System Register (SYSREG) The system register (SYSREG) consists of the 12 nibbles allocated at addresses 74H to 7FH in data memory. The system register (SYSREG) is allocated independently of the banks. This means that each bank has the same system register at addresses 74H to 7FH. Figure 5-2 shows the configuration of the system register. For details, refer to CHAPTER 7 SYSTEM REGISTER (SYSREG). Figure 5-2. System Register Configuration
System register (SYSREG) Address 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Program status word (PSWORD)
Name (Symbol)
Address register (AR)
Window Bank register register (WR) (BANK)
Index register (IX) Data memory row address pointer (MP)
General register pointer (RP)
5.1.2 Data Buffer (DBF) The data buffer consists of four nibbles allocated at addresses 0CH to 0FH in BANK0 of data memory. Figure 5-3 shows the configuration of the data buffer. Figure 5-3. Data Buffer Configuration
Data buffer (DBF) Address Symbol 0CH DBF3 0DH DBF2 0EH DBF1 0FH DBF0
32
CHAPTER 5 DATA MEMORY (RAM)
5.1.3 General Register (GR) The general register consists of 16 nibbles specified by an arbitrary row address in an arbitrary bank in data memory. This arbitrary row address in an arbitrary bank is specified by the register pointer (RP) in the system register (SYSREG). Figure 5-4 shows the configuration of the general register (GR). Figure 5-4. General Register (GR) Configuration
BANK0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F General register Area specifiable as general register Pointed to by general register pointer (RP) in system register. Note that row addresses 0 to 6 of BANK1 are unmounted memory locations. The register pointer (RP) should therefore not specify a row address in this area.
1
Port register
SYSREG
BANK1
Unmounted
Port register
SYSREG
The same register is allocated for each bank.
5.1.4 Port Registers A port register consists of eight nibbles allocated at addresses 70H to 73H in each bank of the data memory. As shown in Figure 5-5, the high-order 3 bits of address 71H of BANK1 and all of addresses 72H and 73H of BANK1 are always set to 0. Figure 5-5 shows the configuration of the port registers. Figure 5-5. Port Register Configuration
Port register Address 70H P0A P BANK0 0 A 3 P 0 A 2 P 0 A 1 P 0 A 0 P 0 B 3 71H P0B P 0 B 2 P 0 B 1 P 0 B 0 P 0 C 3 72H P0C P 0 C 2 P 0 C 1 P 0 C 0 P 0 D 3 73H P0D P 0 D 2 P 0 D 1 P 0 D 0
Symbol
P1A P BANK1 1 A 3 P 1 A 2 P 1 A 1 P 1 A 0
P1B P Fixed to "0" 1 B 0 Fixed to "0" Fixed to "0"
33
CHAPTER 5 DATA MEMORY (RAM)
5.1.5 General Data Memory General data memory is all the data memory not used by the port and system registers (SYSREG). In other words, general data memory consists of 112 nibbles in BANK0. 5.1.6 Unmounted Data Memory There is no hardware mounted at addresses 00H to 6FH of BANK1. Any attempt to read this area will yield undefined value. Writing data to this area is invalid and should therefore not be attempted.
34
CHAPTER 6 STACK
The stack is a register used to save information such as the program return address and the contents of the system register during execution of subroutine calls or interrupts. 6.1 STACK CONFIGURATION Figure 6-1 shows the stack configuration. The stack consists of the following parts: one 3-bit binary counter stack pointer, five 10-bit (PD17134A, 17135A)/ 11-bit (PD17136A, 17137A, 17P136A, 17P137A) address stack registers, and three 6-bit interrupt stack registers. Figure 6-1. Stack Configuration
Stack pointer (SP) b2 SPb2 b1 SPb1 b0 SPb0 0H 1H 2H 3H 4H b10 b9 b8 b7
Address stack register b6 b5 b4 b3 b2 b1 b0
Address stack register 0 Address stack register 1 Address stack register 2 Address stack register 3 Address stack register 4
SP is initialized to 5H at reset
Interrupt stack register 0H BANKSK0 BCDSK0 CMPSK0 1H BANKSK1 BCDSK1 CMPSK1 2H BANKSK2 BCDSK2 CMPSK2
CYSK0 CYSK1 CYSK2 ZSK0 ZSK1 ZSK2 IXESK0 IXESK1 IXESK2
Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 6.2 FUNCTIONS OF THE STACK The stack is used to save the return address during execution of subroutine calls and table reference instructions. When an interrupt occurs, the program return address, bank register (BANK), and the program status word (PSWORD) are automatically saved in the stack.
35
CHAPTER 6 STACK
6.3 ADDRESS STACK REGISTERS (ASRs) Five 11-bit address stack registers (ASRs) are provided as shown in Figure 6-1. The functions of these registers are as follows: * Store a return address when the CALL addr or CALL @AR instruction is executed, when the first instruction cycle of the "MOVT DBF, @AR" instruction is executed, or when an interrupt is accepted. * Store the contents of an address register (AR) when the PUSH AR instruction is executed. The ASR to which the data is to be stored is specified by decrementing the value of the stack pointer (SP) by one when the instruction is executed. * Restore the contents of the ASR (return address) specified by the stack pointer to the program counter and increment the value of the stack pointer by one when the RET or RETSK instruction is executed, when the second instruction cycle of the "MOVT DBF, @AR" instruction is executed, or when the RETI instruction is executed. * Transfer the value of the ASR specified by the stack pointer to an address register and decrement the value of the stack pointer by one when the POP AR instruction is executed. Caution If the stack pointer underflows as a result of executing the CALL addr or CALL @AR instruction or servicing an interrupt, it is assumed that a hang-up occurs. Consequently, the internal reset signal is generated, the hardware is initialized, and the program is started from address 0000H. Remark The size of the ASR differs depending on the model. The PD17134A and 17135A have five 10-bit ASRs, while the PD17136A, 17137A, 17P136A, and 17P137A have five 11-bit ASRs. 6.4 INTERRUPT STACK REGISTERS (INTSKs) Three 5-bit interrupt stack registers (INTSKs) are provided as shown in Figure 6-1. The functions of these registers are as follows: * Five flags (BCD, CMP, CY, Z, and IXE) in the program status word (PSWORD) in the system register (SYSREG) to be explained shortly are saved to the INTSK when an interrupt occurs. After the flags have been saved, all the bits of the BANK and PSWORD are cleared to 0. * The contents of INTSK are restored to the PSWORD when the RETI instruction is executed. * INTSK saves data each time an interrupt has been accepted. Caution If interrupts are accepted exceeding 3 levels, the first data is lost.
36
CHAPTER 6 STACK
6.5 STACK POINTER (SP) AND INTERRUPT STACK REGISTERS The stack pointer is a 3-bit binary counter that specifies the addresses of the five address stack registers as shown in Figure 6-1, and is assigned to address 01H of the register file. The value of the stack pointer is initialized to 5H at reset. * The value of SP is decremented by one when the CALL addr or CALL @AR instruction is executed, when the first instruction cycle of the "MOVT DBF, @AR" instruction is executed, or when an interrupt is accepted. * The value of SP is incremented by one when the RET or RETSK instruction is executed, when the second instruction cycle of the "MOVT DBF, @AR" instruction is executed, when the POP AR instruction is executed, or when the RETI instruction is executed. When an interrupt is accepted, the counter of the interrupt stack registers is also decremented by one in addition to the SP. The value of the counter of the interrupt stack registers is incremented by one only when the RETI instruction is executed. Table 6-1. Operation of Stack Pointer
Instruction CALL addr CALL @AR MOVT, DBF @AR (1st instruction cycle) PUSH AR RET RETSK MOVT DBF, @AR (2nd instruction cycle) POP AR Accepting interrupt RETI Value of stack pointer (SP) Counter of interrupt stack registers
-1 Not affected
+1
-1 +1
-1 +1
Remark Two instruction cycles are required to execute the "MOVT DBF, @AR" instruction, but this is an exception. Because the stack pointer (SP) is a 3-bit binary counter, it can take a value 0H to 7H. If the value of the stack pointer is 6 or more, however, an internal reset signal is generated (to prevent a hang-up). This is because only five address stack registers are available. Because the stack pointer is located on the register file, its value can be directly read by manipulating the register file with the POKE instruction. The value of the stack pointer is also changed at this time, but the values of the address stack registers are not affected. Of course, the stack pointer can also be read by using the PEEK instruction. The value of the stack pointer is 5H at reset.
37
CHAPTER 6 STACK
6.6 STACK OPERATION Stack operation during execution of each instruction is explained in 6.6.1 to 6.6.3. 6.6.1 On Execution of Instructions CALL, RET, RETSK Table 6-2 shows operation of the stack pointer (SP), address stack register, and the program counter (PC) during execution of CALL, RET, and RETSK. Table 6-2. Operation of the Instructions CALL, RET, and RETSK
Instruction CALL addr CALL @AR Operation (1) Stack pointer (SP) is decremented. (2) Program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). (3) Value specified by the instruction operand (addr or @AR) is transferred to the program counter. (1) Value in the address stack register pointed to by the stack pointer (SP) is restored to the program counter (PC). (2) Stack pointer (SP) is incremented.
RET RETSK
When the RETSK instruction is executed, the first instruction after data restoration becomes a NOP instruction. 6.6.2 Table Reference (MOVT DBF, @AR Instruction) Table 6-3 shows the operation during table reference. Table 6-3. Stack Operation during Table Reference
Instruction MOVT DBF, @AR Instruction cycle First Operation (1) Stack pointer (SP) is decremented. (2) Program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). (3) Value in the address register (AR) is transferred to the program counter (PC). Second (4) Contents of the program memory (ROM) pointed to by the program counter (PC) is transferred to the data buffer (DBF). (5) Value in the address stack register pointed to by the stack pointer (SP) is restored to the program counter (PC). (6) Stack pointer (SP) is incremented.
Caution When the "MOVT DBF, @AR" instruction is executed, one level of the address stack is temporarily used. Exercise care not to exceed the usable stack level. Remark Two instruction cycles are required to execute the "MOVT DBF, @AR" instruction. This is an exception.
38
CHAPTER 6 STACK
6.6.3 Operation on Execution of Interrupt Receipt and RETI Instruction Table 6-4 shows stack operation during interrupt receipt and RETI instruction. Table 6-4. Operation during Interrupt Receipt and RETI Instruction
Instruction Receipt of interrupt Operation (1) Stack pointer (SP) is decremented. (2) Value in the program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). (3) Values in the PSWORD flags (BCD, CMP, CY, Z, IXE) are saved in the interrupt stack. (4) Vector address is transferred to the program counter (PC) (1) Values in the interrupt stack register are restored to the PSWORD (BCD, CMP, CY, Z, IXE). (2) Value in the address stack register pointed to by the stack pointer (SP) is restored to the program counter (PC). (3) Stack pointer (SP) is incremented.
RETI
6.7 STACK NESTING LEVELS AND THE PUSH AND POP INSTRUCTIONS During execution of operations such as subroutine calls and returns, the stack pointer (SP) simply functions as a 3-bit counter which is incremented and decremented by one. When the value in the stack pointer is 0H and a CALL or MOVT instruction is executed or an interrupt is received, the stack pointer is decremented to 7H. The PD17134A subseries treat this condition as a fault and generates an internal reset signal. In order to avoid this condition, when the address stack register is being used frequently, the PUSH and POP instructions are used to save the address stack register. Table 6-5 shows stack operation during the PUSH and POP instructions. Table 6-5. Stack Operation during the PUSH and POP Instructions
Instruction PUSH Operation (1) Stack pointer (SP) is decremented. (2) Value in the address register (AR) is transferred to the address stack register pointed to by the stack pointer (SP). (1) Value in the address stack register pointed to by the stack pointer (SP) is transferred to the address register (AR). (2) Stack pointer (SP) is incremented.
POP
39
[MEMO]
40
CHAPTER 7 SYSTEM REGISTER (SYSREG)
The system register (SYSREG), located in data memory, is used for direct control of the CPU. 7.1 SYSTEM REGISTER CONFIGURATION Figure 7-1 shows the allocation address of the system register in data memory. As shown in Figure 7-1, the system register is allocated in addresses 74H to 7FH of data memory, independently of the banks. This means that each bank has the same system register at addresses 74H to 7FH. Since the system register is allocated in data memory, it can be manipulated using any of the data memory manipulating instructions. Therefore, it is also possible to put the system register in the general register. Figure 7-1. Allocation of System Register in Data Memory
Column address 0 0 1
Row address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2 3 4 5 6 7 Port register BANK1 Port register 0 1 2 3 4 5 6 7 Unmounted System register 8 9 A B C D E F Data memory BANK0
Figure 7-2 shows the configuration of the system register. As shown in Figure 7-2, the system register consists of the following seven registers. * Address register * Window register * Bank register * Index register * Data memory row address pointer * General register pointer * Program status word (AR) (WR) (BANK) (IX) (MP) (RP) (PSWORD)
41
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Figure 7-2. System Register Configuration
Address
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH Program status word (PSWORD) PSW
Name
Address register (AR)
Window Bank register register (WR) (BANK)
Index register (IX) Data memory row address pointer (MP) IXH IXM IXL MPH MPL
General register pointer (RP) RPH RPL
Symbol Bit
AR3
AR2
AR1
AR0
WR
BANK
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0
(IX) Data 0 0 0 0 0 Note (AR) M 000 P000 E (BANK) (MP) 000 (RP) BCC I CMY Z X DP E
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 when reset
Note This bit is fixed to 0 in the case of the PD17134A and PD17135A.
42
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.2 ADDRESS REGISTER (AR) 7.2.1 Address Register Configuration Figure 7-3 shows the configuration of the address register. As shown in Figure 7-3, the address register consists of the 16 bits in address 74H to 77H (AR3 to AR0) of the system register. However, since the high-order 5 or 6 bits are always set to 0, the address register is actually 11 or 10 bits. When the system is reset, all 16 bits of the address register are reset to 0. Figure 7-3. Address Register Configuration
Address Name
74H
75H
76H
77H
Address register (AR)
Symbol
AR3
AR2
AR1
AR0
Bit
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
(AR) Data 0 0 0 0 0 Note
Initial value when reset
0
0
0
0
Note This bit is fixed to 0 in the case of the PD17134A and PD17135A. 7.2.2 Address Register Functions The address register is used to specify an address in program memory when executing an indirect branch instruction (BR @AR), indirect subroutine call (CALL @AR) or table reference (MOVT DBF, @AR). The address register can also be put on and taken off the stack by using the stack manipulation instructions (PUSH AR, POP AR). Items (1) to (4) explain address register operation during execution of each instruction. The address register can be incremented by using the dedicated increment instruction (INC AR). (1) Table reference (MOVT DBF, @AR) When the "MOVT DBF, @AR" instruction is executed, the data in program memory (16-bit data) located at the address specified by the value in the address register is read into the data buffer (addresses 0CH to 0FH of BANK0). (2) Stack manipulation instructions (PUSH AR, POP AR) When the PUSH AR instruction is executed, the stack pointer (SP) is first decremented and then the address register is stored in the address stack pointed to by the stack pointer. When the POP AR instruction is executed, the contents of the address stack pointed to by the stack pointer is transferred to the address register and then the stack pointer is incremented. Also see CHAPTER 6 STACK.
43
CHAPTER 7 SYSTEM REGISTER (SYSREG)
(3) Indirect branch instruction (BR @AR) When the BR @AR instruction is executed, the program branches to the address in program memory specified by the value in the address register. (4) Indirect subroutine call (CALL @AR) When the CALL @AR instruction is executed, the subroutine located at the address in program memory specified by the value in the address register is called. (5) Address register used as a peripheral hardware register The address register can be manipulated 4 bits at a time by using data memory manipulation instructions. The address register can also be used as a peripheral hardware register for transferring 16-bit data to the data buffer. In other words, by using the PUT AR, DBF and GET DBF AR instructions, the address register can be used to transfer 16-bit data to the data buffer. Note that the data buffer is allocated in addresses 0CH to 0FH of BANK0 in data memory. Figure 7-4. Address Register Used as a Peripheral Circuit
(BANK0) 0 0 1 1 2 3 4 5
Column address 6789A
B
C
D
E
F
DBF3 DBF2 DBF1DBF0 Data buffer
Row address
2 3 4 5 6 7 AR3 AR2 AR1 AR0 Address register 16-bit data transfer available System register
44
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.3 WINDOW REGISTER (WR) 7.3.1 Window Register Configuration Figure 7-5 shows the configuration of the window register. As shown in Figure 7-5, the window register (WR) consists of four bits allocated at address 78H of the system register. The contents of the window register is undefined after reset. However, when RESET is used to release the system from HALT or STOP mode, the previous state is maintained. Figure 7-5. Window Register Configuration
Address Name Symbol Bit Data Initial value when reset b3
78H Window register WR b2 b1 b0
Undefined
7.3.2 Window Register Functions The window register is used to transfer data to and from the register file (RF). Data is transferred to and from the register file using the dedicated instructions "PEEK WR, rf" and "POKE rf, WR". (1) PEEK WR, rf As shown in Figure 7-6, the "PEEK WR, rf" instruction is used to transfer the contents of the register file specified by rf to the window register. (2) POKE rf, WR As shown in Figure 7-6, the "POKE rf, WR" instruction is used to transfer the contents of the window register to the file specified by rf. Figure 7-6. Example of Window Register Operation
Column address 6789A
0 0 1
1
2
3
4
5
B
C
D
E
F
POKE instruction
Control register Register file
Row address
2 3 4 5 6 7 WR System register PEEK instruction Data memory
45
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.4 BANK REGISTER (BANK) 7.4.1 Bank Register Configuration Figure 7-7 shows the configuration of the bank register. The bank register consists of four bits at address 79H (BANK) of the system register. However, since the three high-order bits are always set to 0, only the least significant bit is actually used. All bits are set to 0 at reset. Figure 7-7. Bank Register Configuration
Address Name
79H Bank register
Symbol
BANK
Bit
b3
b2
b1
b0
Data
0
0
0
(BANK) Initial value when reset 0
7.4.2 Functions of Bank Register The bank register is used to switch between the banks in data memory. Table 7-1 shows how the banks in data memory are specified by the value in the bank register. Table 7-1. Specifying the Bank in Data Memory
Bank register b3 0 0 b2 0 0 b1 0 0 b0 0 1 Bank in data memory BANK0 BANK1
Data memory is effectively divided into two banks by the bank register. When a data memory manipulation instruction is executed, the data memory in the bank specified by the bank register is manipulated. Therefore, if the current bank is BANK0, in order to manipulate data memory in BANK1 (port registers), the bank register must be used to switch the current bank to BANK1. The system register can be manipulated regardless of the state of the bank register. For example, whether the instruction MOV 78H, #0 is executed for BANK0 or BANK1, the effect is the same; 0 is written to address 78H of the system register. In addition, BANK becomes 0 after saved to the interrupt stack register.
46
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP) 7.5.1 Index Register (IX) IX is used for address modification of the data memory. The difference between IX and MP is that IX modifies an address specified by a bank and operand m. IX is allocated to a total of 12 bits of system register addresses 7AH (IXH), 7BH (IXM), and 7CH (IXL), as shown in Figure 7-8. Actually, however, only 11 bits, the low-order 3 bits of IXH, IXM, and IXL, function as IX. An index register enable flag (IXE) which enables address modification by IX is assigned to the least significant bit of PSW. When IXE = 1, the address of the data memory specified by operand m is not m, but the result of ORing between m and IXM through IXL. The bank specified at this time is also indicated by ORing BANK and IXH. Remark IXH of the PD17134A subseries is fixed to "0", and the bank is not modified even when IXE = 1 (to prevent a bank other than 0 from being used). 7.5.2 Data Memory Row Address Pointer (Memory Pointer: MP) MP is used for address modification of the data memory. The difference between IX and MP is that MP modifies the row address of an address indirectly specified by bank and operand @r. MPH and IXH and MPL and IXM are assigned to the same address (addresses 7AH and 7BH of the system register) as shown in Figure 7-8. Actually, however, the low-order 3 bits of MPH and MPL, or a total of 7 bits, function as MP. A memory pointer enable flag (MPE) which enables address modification by MP is assigned to the most significant bit of MPH. When MPE = 1, the bank and row address of the data memory indirectly specified by operand @r are not BANK and mR, but the address specified by MP (the column address is specified by the contents of r independently of MPE). At this time, the low-order 3 bits of MPH and the most significant bit of MPL indicate BANK, and the low-order 3 bits of MPL indicate a row address. Remark The low-order 3 bits of MPH and most significant bit of MPL of the PD17134A subseries are fixed to "0", and bank 0 is always specified even when MPE = 1 (to prevent a bank other than 0 from being used). Figure 7-8. Index Register Configuration
Address Name
7AH
7BH Index register (IX) Memory pointer (MP)
7CH
7FH Low-order 4 bits of program status word (PSWORD)
IXH Symbolic name MPH Bit Flag name b3 M P E b2 b1 b0 b3
IXM MPL b2 b1 b0 b3
IXL PSW b2 b1 b0 b3 b2 b1 b0 I X E
(IX) Data 0 Initial value when reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MP)
47
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Figure 7-9. Modification of Data Memory Address by Index Register and Memory Pointer
Data memory address specified by m IXE MPE b3 Bank b2 b1 b0 Row address Column address b2 b1 b0 b3 b2 b1 b0 b3
Indirect transfer address specified by @r Bank b2 b1 b0 Row address Column address b2 b1 b0 b3 b2 b1 b0
0
0
BANK
m
BANK
mR
(r)
0
1
BANK
m
MPH
MPL
(r)
BANK 1 0 IXH 1 1 Logical OR IXM
m
BANK Logical OR IXL IXH
mR (r) IXM
Setting prohibited
BANK : Bank register IX IXE : Index register : Index enable flag
MP
: Memory pointer
MPE : Memory pointer enable flag MPH : High-order 3 bits of memory pointer MPL : Low-order 4 bits of memory pointer r RP (x) : General register column address : General register pointer : Contents addressed by x x: Direct address such as r
IXH : Bits 10 through 8 of index register IXM : Bits 7 through 4 of index register IXL m mR mC : Bits 3 through 0 of index register : Data memory indicated by mR and mC : Data memory row address : Data memory column address
Table 7-2. Instructions Subject to Address Modification
Arithmetic operation ADD ADDC SUB SUBC Logical operation AND OR XOR Judgment Compare SKT SKF SKE SKGE SKLT SKNE Transfer LD ST MOV r, m m, r
-----------------
r, m
-----------------
m, #n4
r, m
-----------------
m, #n4 m, #n
m, #n4
m, #n4 @r, m m, @r
48
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.5.3 IXE = 0 and MPE = 0 (No Data Memory Modification) As shown in Table 7-9, data memory addresses are not affected by the index register and the data memory row address pointer. (1) Data memory manipulation instructions Example 1. Execution of "ADD r, m" when general register is in row address 0 R003 M061 MEM MEM ADD 0.03H 0.61H R003, M061 ; Addition in memories (0.03H) (0.03H) + (0.61H)
As shown in Figure 7-10, when the above instructions are executed, the data in general register address R003 and data memory address M061 are added together and the result is stored in general register address R003. (2) Indirect transfer of data in the general register (horizontal indirect transfer) Example 2. Execution of "MOV @r, m" when general register is in row address 0 R005 M034 MEM MEM MOV MOV 0.05H 0.34H R005, #8 ; R005 8 (Setting of column address of @r) @R005, M034 ; Indirect transfer of data in the register (0.38H) (0.34H)
As shown in Figure 7-10, when the above instructions are executed, the data stored in data memory address M034 is transferred to data memory location 38H. The "MOV @r, m" instruction transfers the contents of the data memory specified by m to a data memory address with the row address same as m and column address specified by @r. In the above example, therefore, data at M034 is transferred to 38H whose row address is the same as that of M034 (= 3) and column address is specified by the contents of R005 (= 8).
49
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Example 3.
Execution of "MOV m, @r" when general register is in row address 0 R00B M034 MEM MEM MOV MOV 0.0BH 0.34H R00B, #0EH M034, @R00B ; R00B 0EH (Setting column address of @r) ; Indirect transfer of data in the register (0.34H) (0.3EH)
As shown in Figure 7-10, when the above instructions are executed, the contents of data memory stored at address 3EH is transferred to data memory location M034. The "MOV m, @r" instruction transfers the contents of the data memory of the address which the column address is specified by @r to a data memory address specified by m. In the above example, therefore, data at 3EH is transferred to M034 whose row address is the same as that of M034 (= 3) and column address is specified by the contents of R00B (= 0EH). Figure 7-10. Operation Example When IXE = 0 and MPE = 0
Column address 0 0 1
Row address
1
2
3
4
5 8
6
7
8
9
A
B E
C
D
E
F General register
2 3 4 5 6 7
Column address specified as transfer destination Example 2. MOV @R005, M034
Column address specified as transfer source
Example 3. MOV M034, @R00B Example 1. ADD R003, M061
System register
Addresses in Example 1 ADD R003, M061
Addresses in Example 2 MOV @R005, M034
Bank Data memory address M General register address R 0000 0000
Row Column address address 110 000 0001 0011 Data memory address M General register address R Indirect transfer address @R
Bank 0000 0000 0000
Row Column address address 011 000 011 0100 0101 1000 Contents of R
Same as M
50
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.5.4 IXE = 0 and MPE = 1 (Diagonal Indirect Data Transfer) As shown in Figure 7-9, the indirect data transfer bank and row address specified by @r become the data memory row address pointer value only when general register indirect data transfer instructions (MOV @r, m and MOV m, @r) are used. Example 1. Execution of "MOV @r, m" when the general register is in row address 0 R005 MEM M034 MEM MOV MOV MOV MOV 0.05H 0.34H MPL, #0110B MPH, #1000B R005, #8 @R005, M034 ; MP 6 (Setting row address of @r) ; MPE 1, bank 0 ; R005 8 (Setting column address of @r) ; Indirect transfer of data in the register (0.68H) (0.34H)
As shown in Figure 7-11, when the above instructions are executed, the contents of data memory address M034 is transferred to data memory location 68H. When the MOV @r, m instruction is executed when MPE = 1, the contents of the data memory address specified by m is transferred to the column address pointed to by the row address @r being pointed to by the memory pointer. In this case, the indirect address specified by @r becomes the value used for the bank and row address data memory pointer (above example uses row address 6). The column address is the value in the general register address specified by r (above example uses column address 8). Therefore the address in the above example is 68H. This example is different from Example 2 in 7.5.3 when MPE = 0 for the following reasons: In this example, the data memory row address pointer is used to point to the indirect address bank and row address specified by @r. (In Example 2 in 7.5.3, the indirect address bank and row address are the same as m.) By setting MPE = 1, diagonal indirect data transfer can be performed using the general register.
51
CHAPTER 7 SYSTEM REGISTER (SYSREG)
2. Execution of "MOV m, @r" when general register is in row address 0 R00B M034 MEM MEM MOV MOV MOV MOV 0.0BH 0.34H MPL, #0110B MPH, #1000B R00B, #0EH M034, @R00B ; MP 6 (Setting row address of @r) ; MPE 1, bank 0 ; R00B 0EH (Setting column address of @r) ; Indirect transfer of data in the register (0.34H) (0.6EH)
As shown in Figure 7-11, when the above instructions are executed, the data stored in address 6EH is transferred to data memory location M034. Figure 7-11. Operation Example When IXE = 0 and MPE = 1
Column address 6 7 8 9
0 0 1
1
2
3
4
5 8
A
B E
C
D
E
F General register
Column address specified as transfer destination
Column address specified as transfer source
Row address
2 3 4 5 Example 1. MOV @R005, M034 6 7 System register Memory pointer = 00110B Example 2. MOV M034, @R00B
Addresses in Example 1 MOV @R005, M034
Addresses in Example 2 MOV M034, @R00B
Bank Data memory address M General register address R Indirect transfer address @R 0000 0000 0000
Row
Column
address address 011 000 110 0100 0101 1000 Contents of R Data memory address M General register address R Indirect transfer address @R
Bank 0000 0000 0000
Row
Column
address address 011 000 110 0100 1011 1110 Contents of R
Contents of MP
Contents of MP
52
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.5.5 IXE = 1 and MPE = 0 (Index Modification) As shown in Figure 7-9, when a data memory manipulation instruction is executed, any bank or address in data memory specified by m can be modified using the index register. When indirect data transfer using the general register (MOV @r, m or MOV m, @r) is executed, the indirect transfer bank and address specified by @r can be modified using the index register. Address modification is done by performing an OR operation on the data memory address and the index register. The data memory manipulation instruction being executed manipulates data in the memory location pointed to by the result of the operation (called the real address). An example is shown below. Example 1. Execution of "ADD r, m" when the general register is in row address 0 R003 M061 MEM MEM MOV MOV MOV OR ADD 0.03H 0.61H IXL, #0010B IXM, #0001B IXH, #0000B R003, M061 ; IX 00000010010B ; ; MPE 0 ; (0.03H) (0.03H) + (0.73H)
PSW, #.DF.IXE AND 0FH ; IXE 1
As shown in Figure 7-12, when the instructions of example 1 are executed, the value in data memory address 73H (real address) and the value in general register address R003 (address 03H) are added together and the result is stored in general register address R003. When the ADD r, m instruction is executed, the data memory address specified by m (address 61H in above example) is index modified. Modification is done by performing an OR operation on data memory location M061 (address 61H, binary 00001100001B) and the index register (00000010010B in the above example). The result of the operation (00001110011B) is used as a real address (address 73H) by the instruction being executed. As compared to when IXE = 0 (Examples in 7.5.3), in this example the data memory address being directly specified by m is modified by performing an OR operation on m and the index register.
53
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Figure 7-12. Operation Example When IXE = 1 and MPE = 0
Column address 6 7 8 9
0 0 1
Row address
1
2
3
4 R003
5
A
B
C
D
E
F General register
Example 1. ADD R003, M061 Index modification M061 : 00001100001B : 00000010010B OR) IX Real address 00001110011B M061
2 3 4 5 6 7
System register
Addresses in Example 1 ADD R003, M061
Bank Data memory address M General register address R Index modification M061 0000 0000 0000 BANK IX 0000 IXH Real address (OR operation) 0000
Column address address Row 110 000 110 m 001 IXM 111 0010 IXL 0011 Instruction is executed using this address. 0001 0011 0001
54
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Example 2. Indirect data transfer using the general register (Execution of "MOV @r, m") R005 MEM M034 MEM MOV MOV MOV OR MOV MOV 0.05H 0.34H IXL, #0001B IXM, #0000B IXH, #0000B R005, #8 @R005, M034 ; Column address 5 (OR of 4 and 1) ; Row address 3 (OR of 3 and 0) ; MPE 0, bank 0 (OR of 0 and 0) ; R005 8 (Setting column address of @r) ; Indirect data transfer using the register ; (0.38H) (0.35H) As shown in Figure 7-13, when the above instructions are executed, the contents of data memory address 35H is transferred to data memory location 38H. When the MOV @r, m instruction is executed when IXE = 1, the data memory address specified by m (direct address) is modified using the contents of the index register. The bank and row address of the indirect address specified by @r are also modified using the index register. The bank, row address, and column address specified by m (direct address) are all modified, and the bank and row address specified by @r (indirect address) are modified. Therefore, in the above example the direct address is 35H and the indirect address is 38H. This example is different from Example 3 in 7.5.3 when IXE = 0 for the following reasons: In this example, the bank, row address and column address of the direct address specified by m are modified using the index register. The general register is transferred to the address specified by the column address of the modified data memory address and the same row address. (In Example 3 in 7.5.3, the direct address is not modified.) Figure 7-13. Operation Example When IXE = 1 and MPE = 0
PSW, #.DF.IXE AND 0FH ; IXE 1
0 0 1
1
2
3
4
5 8
Column address 6 7 8 9 R005
A
B
C
D
E
F General register
Row address
2 3
M034
Column address specified as transfer destination Example 2. MOV @R005, M034 Indirect address
Direct 4 Index modification address M034 : 00000110100B 5 : 00000000001B OR) IX 6 Real address 00000110101B 7
System register
55
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Example 3. Clearing data memory of 00H-0FH to 0 M000 MEM MOV MOV MOV LOOP: OR MOV INC AND SKE BR PSW, #.DF.IXE AND 0FH ; IXE 1 M000, #0 IX PSW, #1110B IXM, #7 LOOP ; Set data memory specified by IX to 0 ; IX IX + 1 ; IXE 0, Remains address 7FH even if modified ; by IX because IXE is address 7FH. ; Row address 7 ? ; If not 7 then LOOP (row address is not cleared) 0.00H IXL, #0 IXM, #0 IXH, #0 ; IX 0 ; ; MPE 0
4. Processing an array As shown in Figure 7-14, when an operation A(N) A(N) + 4 (0 N 15) is executed to element A (N) of a one-dimensional array with each element 8 bits long, the following instructions are executed. M000 MEM M001 MEM MOV MOV MOV OR ADD ADDC 0.00H 0.01H IXH, #0 IXM, #N SHR 3 IXL, #N SHL 1 AND 0FH M000, #4 M001, #0 ; A(N) A(N) + 4 ; Sets offset of row address ; Sets offset of column address
PSW, #.DF.IXE AND 0FH ; IXE 1
In the above example, the value of N shifted 1 bit to the left (i.e., the value of N multiplied by 2) is set to the index register because one element is 8 bits long. Figure 7-14. Operation Example When IXE = 1 and MPE = 0 (Array Processing)
Column address 7 8 9 A (4) A (12)
0 0 1
1
2
3
4
5
6
A
B
C
D
E
F
A (0) A (8)
A (1) A (9)
A (2) A (10)
A (3) A (11) A (0)
A (5) A (13)
A (6) A (14)
A (7) A (15)
Row address
2 3 00H 4 b3 5 6 7 System register b2 b1 b0 b7 b6 b5 b4 01H
56
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.6 GENERAL REGISTER POINTER (RP) 7.6.1 General Register Pointer Configuration Figure 7-15 shows the configuration of the general register pointer. Figure 7-15. General Register Pointer Configuration
Address Name Symbol Bit b3
7DH General register pointer (RP) RPH b2 b1 b0 b3
7EH
RPL b2 b1 b0 B
Flag
C D 0 0 0 (RP) 0 0
Data Initial value when reset
As shown in Figure 7-15, the general register pointer consists of seven bits; four bits in system register address 7DH (RPH) and the high-order 3 bits of system register address 7EH (RPL). However, since the high-order 3 bits of address 7DH are always set to 0, the register effectively consists of four bits; the least significant bit of address 7DH and the high-order 3 bits of address 7EH. All register bits are cleared to 0 at reset.
57
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.6.2 Functions of the General Register Pointer The general register pointer is used to specify the location of the general register in data memory. For the general register, see CHAPTER 8 GENERAL REGISTER (GR). The general register consists of 16 nibbles in any single row of data memory. As shown in Figure 7-16, the general register pointer is used to indicate which row address is being used as the general register. Since the general register pointer effectively consists of four bits, the data memory row addresses in which the general register can be placed are address 0H to 7H of BANK0 and BANK1. In other words, any row in data memory can be specified as the general register. With the general register allocated in data memory, data can be transferred to and from, and arithmetic operations can be performed on the general register and data memory. Note that row addressed 0H to 6H of BANK1 are unmounted memory locations and should therefore not be specified as locations for the general register. For example, when instructions such as ADD r,m and LD r,m are executed, instruction operand r can specify an address in the general register and m specifies an address in data memory. In this way, operations like addition and data transfer can be performed on and between data memory and the general register. Figure 7-16. General Register Configuration
General register pointer (RP) RPH b3 b2 b1 b0 0 0 0 0 0 0 0 0 b3 0 0 0 0 1 1 1 1 RPL b2 0 0 1 1 0 0 1 1 b1 0 1 0 1 0 b0 0 1 2 3 4 General register (16 nibbles) Example General register with RP = 0000010B Area in which general register can be specified BANK0 0 1 2 3 4 5 Column address 6 7 8 9 A B C D E F
Fixed to 0
Fixed to 0
Fixed to 0
Allocated to the flag BCD
1 0 1
5 6 7 BANK1 0 1 2 3 4 5 6 7 Port register System register Unmounted Both banks have the same system register. System register RP
1 1 This area should not be used. 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
58
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.7 PROGRAM STATUS WORD (PSWORD) 7.7.1 Program Status Word Configuration Figure 7-17 shows the configuration of the program status word. Figure 7-17. Program Status Word Configuration
Address Name Symbol Bit b3
7EH
7FH Program status word (PSWORD) PSW b0 B C D b3 C M P b2 C Y b1 Z b0 I X E
(RP) RPL b2 b1
Data
Initial value when reset
0
0
As shown in Figure 7-17, the program status word consists of five bits; the least significant bit of system register address 7EH (RPL) and all four bits of system register address 7FH (PSW). The program status word is divided into the following 1-bit flags: Binary coded decimal flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and the index enable flag (IXE). All register bits are cleared to 0 at reset and after the contents of the interrupt stack register have been saved.
59
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.7.2 Functions of the Program Status Word The flags of the program status word are used for setting conditions for arithmetic operations and data transfer instructions and for reflecting the status of operation results. Figure 7-18 shows an outline of the functions of the program status word. Figure 7-18. Outline of Functions of the Program Status Word
Address Bit Symbol Flag
7EH
7FH
b3 b2 b1 b0 b3 b2 b1 b0 RPL PSW BCCZI CM Y DP X E
Flag
Function Used to specify that index modification be performed on the data memory address used when a data memory manipulation instruction is executed. 0: Index modification disabled. 1: Index modification enabled. Set when the result of an arithmetic operation is 0. 0: Indicates that the result of the arithmetic operation is a value other than 0. 1: Indicates that the result of the arithmetic operation is 0. Set when there is a carry in the result of an addition operation or a borrow in the result of a subtraction operation. 0: Indicates there was no carry or borrow. 1: Indicates there was a carry or borrow. Used to specify that the result of an arithmetic operation not be stored in data memory or the general register but just be reflected in the CY and Z flags. 0: Results of arithmetic operations are stored. 1: Results of arithmetic operations are not stored. Used to specify how arithmetic operations are performed. 0: Arithmetic operations are performed in 4-bit binary. 1: Arithmetic operations are performed in BCD.
IXE
Z
CY
CMP
BCD
60
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.7.3 Index Enable Flag (IXE) The IXE flag is used to specify index modification on the data memory address when a data memory manipulation instruction is executed. When the IXE flag is set to 1, an OR operation is performed on the data memory address and the index register (IX), and executes an instruction to the data memory with the result of the OR operation as the real address. For a more detailed explanation, see 7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP). 7.7.4 Zero Flag (Z) and Compare Flag (CMP) The Z flag indicates that the result of an arithmetic operation is 0. The CMP flag is used to specify that the result of an arithmetic operation not be stored in data memory or the general register. Table 7-3 shows how the CMP flag affects the setting and resetting of the Z flag. Table 7-3. Zero Flag (Z) and Compare Flag (CMP)
Conditions When the result of an arithmetic operation is a value 0 When the result of an arithmetic operation is other than 0 When CMP flag Z1 Z0 When CMP flag is 1 Z flag remains unchanged Z0
The Z flag and the CMP flag are used for comparing values in the general register and data memory. The Z flag is only affected by arithmetic operations. The CMP flag is only affected by bit evaluation. Example of comparing 12-bit data ; Are 12-bit data stored in M001, M002, and M003 equal to 456H? CMP456: SET2 SUB SUB SUB ; CLR1 SKT1 BR BR 7.7.5 Carry Flag (CY) The CY flag shows that there is a carry in the result of an addition operation or a borrow in the result of a subtraction operation. The CY flag is set (CY = 1) when there is a carry or borrow in the result and reset (CY = 0) when there is no carry or borrow in the result. When the RORC r instruction (contents in the general register specified to by r is shifted right one bit) is executed, the following occurs: the value in the CY flag just before execution of the instruction is shifted to the most significant bit of the general register and the least significant bit is shifted to the CY flag. The CY flag is also useful for when the user wants to skip the next instruction when there is a carry or borrow in the result of an operation. The CY flag is only affected by arithmetic operations and rotations and not affected by the CMP flag. CMP, Z M001, #4 M002, #5 M003, #6 CMP Z DIFFER AGREE ; 456 H ; = 456 H ; CMP is automatically cleared by bit judgement instruction ; Data stored to M001, M002, and M003 are not lost
61
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.7.6 Binary-Coded Decimal Flag (BCD) The BCD flag is used for BCD operations. When the BCD flag is set (BCD = 1), all arithmetic operations will be performed in BCD. When the BCD flag is reset (BCD = 0), arithmetic operations are performed in 4-bit binary. The BCD flag does not affect logical operations, bit judgement, comparison judgement or rotations. 7.7.7 Notes Concerning Use of Arithmetic Operations When performing arithmetic operations (addition and subtraction) on the program status word (PSWORD), the following point should be kept in mind. When an arithmetic operation is performed on the program status word, the result is stored in the program status word. Below is an example. Example MOV ADD PSW, #0001B PSW, #1111B
When the above instructions are executed, a carry is generated which should cause bit 2 (CY flag) of PSW to be set. However, the result of the operation (0000B) is stored in PSW, meaning that CY does not get set.
62
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.8 NOTES CONCERNING USE OF THE SYSTEM REGISTER 7.8.1 Reserved Words for the System Register Because the system register is allocated in data memory, it can be used in any of the data memory manipulation instructions. As shown in Example 1 (using a 17K Series Assembler AS17K), because a data memory address can not be directly coded in an instruction operand, it needs to be defined as a symbol beforehand. The system register is data memory, but has specialized functions which make it different from general-purpose data memory. Therefore, the system register is used by defining it beforehand with symbols (used as reserved words) in the assembler (AS17K). Reserved words for the system register are allocated in address 74H to 7FH. They are defined by the symbols (AR3, AR2, ..., PSW) shown in Figure 7-2. As shown in Example 2, if these reserved words are used, it is not necessary to define symbols. For information concerning reserved words, see CHAPTER 20 ASSEMBLER RESERVED WORDS. Example 1. M037 MOV MOV MOV 2. MOV 34H, #0101B 76H, #1010B ; Using a data memory address like 34H or 76H will cause an ; error in the assembler. ; Addresses in general data memory need to be defined as
MEM 0.37H
M037, #0101B ; symbols using the MEM directive. AR1, #1010B ; By using the reserved word AR1 (address 6H), there is no need ; to define the address as a symbol. ; Reserved word AR1 is defined in a device file with the directive ; "AR1 MEM 0.76H".
Assembler AS17K has the below flag symbol manipulation instructions defined internally as macros. SETn CLRn SKTn SKFn NOTn INITFLG : Set a flag to 1 : Reset a flag to 0 : Skip when all flags are 1 : Skip when all flags are 0 : Invert a flag : Initialize a flag
By using these embedded macro instructions, data memory can be handled as flags as shown below in Example 3. The functions of the program status word and the memory pointer enable flag are defined in bit units (flag units) and each bit has a reserved word defined for it. These reserved words are MPE, BCD, CMP, CY, Z and IXE. If these flag reserved words are used, the embedded macro instructions can be used as shown in Example 4.
63
CHAPTER 7 SYSTEM REGISTER (SYSREG)
Example 3. F0003
FLG 0.00.3 SET1 F0003
; Flag symbol definition ; Embedded macro
Expanded macro OR .MF.F0003 SHR 4, #.DF.F0003 AND 0FH ; Set bit 3 of address 00H of BANK0
4.
SET1
BCD Expanded macro
; Embedded macro
OR
.MF.BCD SHR 4, #.DF.BCD AND 0FH ; Set the BCD flag ; BCD is defined as "BCD FLG 0.7EH.0"
CLR2 Z, CY Expanded macro AND
; Identical address flag
.MF.Z SHR 4, #.DF. (NOT (Z OR CY) AND 0FH)
CLR2 Z, BCD Expanded macro AND AND
; Different address flag
.MF.Z SHR 4, #.DF. (NOT Z AND 0FH) .MF.BCD SHR 4, #.DF. (NOT BCD AND 0FH)
64
CHAPTER 7 SYSTEM REGISTER (SYSREG)
7.8.2 Handling of System Register Addresses Fixed at 0 In dealing with system register area fixed at 0 (see Figure 7-2), there are a few points for which caution should be taken with regard to device, emulator and assembler operation. Items (1), (2) and (3) explain these points. (1) Concerning device operation Trying to write data to an address fixed at 0 will not change the value (0) at that address. Any attempt to read an address fixed at 0 will result in the value 0 being read. (2) When using a 17K series in-circuit emulator (IE-17K or IE-17K-ET) An error will be generated if a write instruction attempts to write 1 to an address fixed at 0. Below is an example of the type of instructions that will cause the in-circuit emulator to generate an error. Example 1. 2. MOV MOV MOV MOV ADD ADDC ADDC BANK, #0100B IXL, #1111B IXM, #1111B IXH, #0001B IXL, #1 IXM, #0 IXH, #0 ; Attempts to write 1 to bit 3 (an address fixed at 0). ; ; ; Attempts to write 1 to bit 0 (an address fixed at 0). ; ; ; Attempts to write 1 to bit 0 (an address fixed at 0) as a result of operation. However, when all valid bits are set to 1 as shown in Example 2, executing the instructions INC AR or INC IX will not cause an error to be generated by the in-circuit emulator. This is because when all valid bits of the address register and index register are set to 1, executing the INC instruction causes all bits to be set to 0. The only time the in-circuit emulator will not generate an error when an attempt is made to write the value 1 to an address fixed at 0 is when the address being written to is in the address register. (3) When using a 17K series assembler (AS17K) No error is output when an attempt is made to write 1 to an address fixed at 0. The instruction shown in Example 1 MOV BANK, #0100B will not cause an assembler error. However, when the instruction is executed in the in-circuit emulator, an error is generated. The following is the reason why an error is not generated in the assembler: the assembler does not know what data memory address is the object of the data memory manipulation instruction being executed. The assembler generates an error only when the value n in the embedded macro BANKn is a value greater than 2: This is because the assembler judges that embedded macros other than BANK0 and 1 cannot be used in the
PD17134A subseries.
65
[MEMO]
66
CHAPTER 8 GENERAL REGISTER (GR)
The general register (GR) is allocated in data memory. It can therefore be used directly for arithmetic operations and transferring data. 8.1 GENERAL REGISTER CONFIGURATION Figure 8-1 shows the configuration of the general register. As shown in Figure 8-1, 16 nibbles in a single row address in data memory (16 x 4 bits) are used as the general register. The register pointer (RP) in the system register is used to indicate which row address is to be used as the general register. Since the general register pointer effectively has four valid bits, the data memory row addresses in which the general register can be allocated are addresses 0H to 7H of BANK0 and BANK1. However, note that row addresses 0H to 6H of BANK1 are unmounted area and should therefore not be specified as locations for the general register. 8.2 FUNCTIONS OF THE GENERAL REGISTER The general register can be used in transferring data to and from data memory and in performing arithmetic operations with data memory within an instruction. In effect, since the general register is data memory, this just means that operations such as arithmetic operations and data transfer can be performed on and between locations in data memory. In addition, because the general register is allocated in data memory, it can be controlled in the same manner as other areas in data memory through the use of data memory manipulation instructions.
67
CHAPTER 8 GENERAL REGISTER (GR)
Figure 8-1. General Register Configuration
BANK0 01 0 1 The general register pointer (RP) can be used to specify any row address in address locations 0H to 7H of BANK0 and BANK1. However, note that row addresses 0H to 6H of BANK1 are unmounted memory locations and should therefore not be specified.
Row address
2
3
4
5
Column address 6789A
B
C
D
E
F
2 3 4 5 6 7
General Register (16 nibbles)
General register when RP = 00010B
System register
RP
BANK1 0 1 2 3 4 5 6 7 System register Unmounted (Row addresses 0H to 6H of BANK1 are unmounted memory locations. RP should therefore not specify a row address in this area). Both banks have the same system register.
Address Name Symbol Bits
7DH
7EH
General register pointer (RP) RPH RPL
b3 b2 b1 b0 b3 b2 b1 b0 B C D
Data
0
0
0
Reset
0
0
0
0
0
0
0
68
CHAPTER 9 REGISTER FILE (RF)
The register file is a register used mainly for specifying conditions for peripheral hardware. 9.1 REGISTER FILE CONFIGURATION 9.1.1 Configuration of the Register File Figure 9-1 shows the configuration of the register file. As shown in Figure 9-1, the register file is a register consisting of 128 nibbles (128 words x 4 bits). In the same way as with data memory, the register file is divided into addresses in 4-bit units. It has a total of 128 nibbles specified in row addresses from 0H to 7H and column addresses from 0H to 0FH. Address 00H to 3FH define an area called the control register. 9.1.2 Relationship between the Register File and Data Memory Figure 9-2 shows the relationship between the register file and data memory. As shown in Figure 9-2, the register file overlaps with data memory in addresses 40H to 7FH. This means that the same memory exists in register file addresses 40H to 7FH and in data memory bank addresses 40H to 7FH. Assuming that the current bank is BANK0, register file addresses 40H to 7FH are equivalent to addresses 40H to 7FH of BANK0 in data memory. When the current bank is BANK1, register file addresses 40H to 7FH are equivalent to address 40H to 7FH of BANK1 in data memory. Figure 9-1. Register File Configuration
Column address 0123456789ABCDEF 0 1
Row address
2 3 4 5 6 7
Control register
Register file
69
CHAPTER 9 REGISTER FILE (RF)
Figure 9-2. Relationship Between the Register File and Data Memory
Column address 012 34 56 789ABCDEF 0 1
Row address
Data memory
2 3 4 5 6 7 Port register Port register System register 0 1 2 3 Control register BANK0 BANK1
Unmounted
Register file
9.2 FUNCTIONS OF THE REGISTER FILE 9.2.1 Functions of the Register File The register file is mainly used as a control register for specifying conditions for peripheral hardware. This control register is allocated within the register file at addresses 00H to 3FH. The rest of the register file (40H to 7FH) overlaps with data memory. As shown in 9.2.3, because of this overlap, this area of the register file is the same as normal memory with one exception: The register file manipulation instructions PEEK and POKE can be used with this area of memory but not with normal data memory. 9.2.2 Functions of Control Register The peripheral hardware whose conditions can be controlled by control registers is listed below. For details concerning peripheral hardware and the control register, see the section for the peripheral hardware concerned. * Stack pointer (SP) * Power-down reset * 8-bit timer counter (TM0, TM1) * AC zero cross detector (ZCROSS) * A/D converter * Basic interval timer (BTM) * Ports * Interrupt functions * Serial interface (SIO)
70
CHAPTER 9 REGISTER FILE (RF)
9.2.3 Register File Manipulation Instructions Reading and writing data from and to the register file is done using the window register (WR: address 78H) located in the system register. Reading and writing of data is performed using the following dedicated instructions: PEEK WR, rf: Read the data in the address specified by rf and put it into WR. POKE rf, WR: Write the data in WR into the address specified by rf. Below is an example using the PEEK and POKE instructions. Example RF02 RF1F RF53 RF6D RF70 RF71 BANK0 1 2 3 4 5 6 7 8 PEEK POKE PEEK POKE BANK1 PEEK POKE PEEK POKE WR, RF02 RF1F, WR WR, RF70 RF72, WR ; ; ; ; WR, RF02 RF1F, WR WR, RF53 RF6D, WR ; ; ; ; ; MEM0.82H MEM0.9FH MEM0.53H MEM0.6DH MEM1.70H MEM1.71H ; Symbol definition ; Register file addresses 00H to 3FH must be defined with ; symbols as BANK0 addresses 80H to BFH. ; See 9.4 NOTES CONCERNING USE OF THE REGISTER FILE ; for details. ;
Figure 9-3 shows an example of register file operation. As shown in Figure 9-3, reading and writing of data to and from the control register (addresses 00H to 3FH) is performed using the "PEEK WR, rf" and "POKE rf, WR" instructions. Data within the control register specified using rf can be read from and written to the control register, only by using these instructions with the window register. The fact that the register file overlaps with data memory in addresses 40H to 7FH has the following effect: When a "PEEK WR, rf" or "POKE rf, WR" instruction is executed, the effect is the same as if they were being executed on the data memory address (in the current bank) specified by rf. Addresses 40H to 7FH of the register file can be operated by normal memory manipulation instructions.
71
CHAPTER 9 REGISTER FILE (RF)
Figure 9-3. Accessing the Register File Using the PEEK and POKE Instructions
Column address 0 0 1
Row address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data memory
2 3 4 5 6 7
BANK0
3 PEEK WR, RF53
4 POKE RF6D, WR
3 4 5 6 7
BANK1 Unmounted 7 PEEK WR, RF70 8 POKE RF72, WR
WR
System register
0 1 2 3 1 5 PEEK WR, RF02 2 6 POKE RF1F, WR Control register Register file for BANK0
Register file for BANK1
9.3 CONTROL REGISTER Figure 9-4 shows the configuration of the control register. As shown in Figure 9-4, the control register consists of 64 nibbles (64 ! 4 bits) allocated in register file addresses 00H to 3FH. However, only 26 nibbles are actually used. The remaining 38 nibbles are allocated for registers which have not yet been implemented. Data should not be read from or written to this area. There are two types of registers, both of which occupy one nibble of memory. One type is read/write (R/W), and the other is read-only (R). Note that within the read/write (R/W) flags, there exists a flag that will always be read as 0. The following read/write (R/W) flags are those flags which will always be read as 0:
72
CHAPTER 9 REGISTER FILE (RF)
* WDTRES (RF: 03H, bit 3) * WDTEN * TM0RES * TM1RES * BTMRES (RF: 03H, bit 0) (RF: 11H, bit 2) (RF: 12H, bit 2) (RE: 13H, bit 2)
* ADCSTRT (RF: 20H, bit 0) Within the four bits of data in a nibble, there are bits which are fixed at 0 and will therefore always be read as 0. These bits remain fixed at 0 even when an attempt is made to write to them. Attempting to read data in the unused register address area (38 nibbles) will yield unpredictable values. In addition, attempting to write to this area has no effect. 9.4 NOTES CONCERNING USE OF THE REGISTER FILE 9.4.1 Notes Concerning Operation of the Control Register (Read-Only and Unused Registers) It is necessary to take note of the following notes concerning device operation and use of the 17K Series assembler (AS17K) and in-circuit emulator (IE-17K or IE-17K-ET) with regard to the read-only (R) and unused registers in the control register (register file addresses 00H to 3FH). (1) Device operation Writing to a read-only register has no effect. Attempting to read data from an address in the unused data area will yield an undefined value. Attempting to write to an address in the unused data area has no effect. (2) During use of the assembler (AS17K) An error will be generated if an attempt is made to write to a read-only register. An error will also be generated if an attempt is made to read from or write to an address in the unused data area. (3) During use of the in-circuit emulator (IE-17K or IE-17K-ET) (operation during patch processing and similar operations) Attempting to write to a read-only register has no effect. No error is generated. Attempting to read data from an address in the unused data area will yield an undefined value. Attempting to write to an address in the unused data area has no effect. No errors are generated. 9.4.2 Register File Symbol Definitions and Reserved Words Attempting to use a numerical value in a 17K Series assembler (AS17K) to specify a register file address in the rf operand of the "PEEK WR, rf" or "POKE rf, WR" instructions will cause an error to be generated. Therefore, as shown in Example 1, register file addresses need to be defined beforehand as symbols. Example 1. Case which causes an error to be generated PEEK POKE WR, 02H 21H, WR ; ;
Case in which no error is generated RF71 MEM0.71H ; Symbol definition PEEK WR, RF71 ;
73
CHAPTER 9 REGISTER FILE (RF)
Caution should especially be taken with regard to the following point: * When using a symbol to define the control register as an address in data memory, it needs to be defined as addresses 80H to BFH of BANK0. Since the control register is manipulated using the window register, any attempt to manipulate the control register other than by using the "PEEK" and "POKE" instructions needs to cause an error in the assembler. However, note that any address in the area of the register file overlapping with data memory (addresses 40H to 7FH) can be defined as a symbol in the same manner as with normal data memory. An example is given below. Example 2. RF71 RF02 MEM MEM BANK0 PEEK PEEK BANK1 PEEK PEEK WR, RF71 WR, RF02 ; RF71 becomes address 71H in BANK1. ; RF02 becomes address 02H in the control register. WR, RF71 WR, RF02 ; RF71 becomes address 71H in BANK0. ; RF02 becomes address 02H in the control register. 1.71H 0.82H ; Register file overlapping with data memory ; Control register
The assembler (AS17K) has the below flag symbol manipulation instructions defined internally as macros. SETn CLRn SKTn SKFn NOTn INITFLG : Set a flag to 1 : Reset a flag to 0 : Skip when all flags are 1 : Skip when all flags are 0 : Invert a flag : Initialize a flag
By using these embedded macro instructions, the contents of the register file can be manipulated in 1-bit unit. Due to the fact that most of control register consists of 1-bit flags, the assembler (AS17K) has reserved words for use with these flags. However, note that there is no reserved word for the stack pointer for its use as a flag. The only reserved word used for the stack pointer is the reserved word "SP", for its use as data memory. For this reason, none of the above flag manipulation instructions can be used with the stack pointer.
74
CHAPTER 9 REGISTER FILE (RF)
Figure 9-4. Control Register Configuration (1/2)
Column address Row address Item 0 1 S P Symbol 0 (8) When reset Read/ Write P D R 0E S E N 0 0 T M 0 E N 0 1 0 1 0 2 SSSSW IIIID OOOOT THCCR0 SIKKE Z10S 0 0 0 0 0 0 3 W D T 0E N 4 5 6 7
0
0
R/W
R/W
R/W
Symbol 1 (9)
0
0
T M 0 R E S 0
T M 0 C K 1 0
T M 0 C K 0 0
T M 1 E N
T M 1 R E S 0
T M 1 C K 1 0
T M 1 C K 0 0
B T M I S E L 0
B T M R E S 0
B T M C K 1 0
B T M C K 0 0
When reset 0 Read/ Write
0
0
1
R/W
R/W
R/W
R/W
Symbol 2 (A)
0
0
A D C 0S T R T 0 0
A AA D DD C CC S0CE O MN F PD T 0 0 0 R 0
A D C C H 3 0
A D C C H 2 0
A D C C H 1 0
A D C C H 0 0
When reset 0 Read/ Write
0
R/W
R/W
R/W
Symbol 3 (B) When reset Read/ Write
Remark The address in parentheses apply when the AS17K assembler is used. The names of all the flags in the control registers are assembler reserved words saved in the device file. Using these reserved words is useful in programming. (See CHAPTER 20 ASSEMBLER RESERVED WORDS.)
75
CHAPTER 9 REGISTER FILE (RF)
Figure 9-4. Control Register Configuration (2/2)
8
9
A T M 0 O0 S E L 0 0
B S I O 0E0 N
C P 0 B 0G P U P 0 A G P U
D
E
F I N T 0 0 0
0
0
0
0
0
0
0
0 R
0
Note
R/W
R/W
P 0 C 3 I D I 0
P 0 C 2 I D I 0
P 0 C 1 I D I 0
P 0 C 0 I D I 0
P 0 C B I O 3 0
P 0 C B I O 2 0
P 0 C B I O 1 0
P 0 C B0 I O 0 0 0
0
Z C R 0O S S 0 0
0
I E G 0M D 1 0 0
I E G M D 0 0
0
0
R/W
R/W
R/W
R/W
P 0 D B I O 3 0
P 0 D B I O 2 0
P 0 D B I O 1 0
P P 1 0 A D B0G I I O O 0 0 0 0
P 0 B G I O 0
P 0 A G I O 0
0
0
I P S 0I O
I P B T M
I P T M 1
II PP T M 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
0
0
I R Q 0S0 I O 0 0 0
0
I R Q 0B0 T M
0
I R Q 0T0 M 1 0
0
I R Q 0T0 M 0 0 0 0
I R Q 0 0
0
0
0
0
0
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Note The value of the INT flag changes every moment according to the status of the INT pin.
76
CHAPTER 10 DATA BUFFER (DBF)
The data buffer consists of four nibbles allocated in addresses 0CH to 0FH in BANK0. The data buffer acts as a data storage area for the CPU peripheral circuit (address register, serial interface, timer 0, timer1, basic internal timer, and A/D converter) through use of the GET and PUT instructions. It also acts as data storage used for receiving and transferring data. By using the MOVT, DBF, and @AR instructions, fixed data in program memory can be read into the data buffer. 10.1 DATA BUFFER CONFIGURATION Figure 10-1 shows the allocation of the data buffer in data memory. As shown in Figure 10-1, the data buffer is allocated in address locations 0CH to 0FH in BANK0 and consists of a total of 16 bits (4 x 4 bits). Figure 10-1. Allocation of the Data Buffer
Column address 0 0 1 Data memory
Row address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data buffer (DBF)
2 3 4 5 6 7 System register (SYSREG) BANK0
Figure 10-2 shows the configuration of the data buffer. As shown in Figure 10-2, the data buffer is made up of 16 bits with its LSB in bit 0 of address 0FH and its MSB in bit 3 of address 0CH. Figure 10-2. Data Buffer Configuration
Data memory BANK0
Address Bit Bit b3
0CH b2 b1 b0 b3
0DH b2 b1 b0 b8 b3 b7
0EH b2 b6 b1 b5 b0 b4 b3 b3
0FH b2 b2 b1 b1 b0 b0
b15 b14 b13 b12 b11 b10 b9 DBF3 ^ M S B ^ Data DBF2
Data buffer Symbol DBF1 DBF0 ^ L S B
Data
Because the data buffer is allocated in data memory, it can be used in any of the data memory manipulation instructions.
^
77
CHAPTER 10 DATA BUFFER (DBF)
10.2 FUNCTIONS OF THE DATA BUFFER The data buffer has two separate functions. The data buffer is used for data transfer with peripheral hardware. The data buffer is also used for reading constant data (table reference) in program memory. Figure 10-3 shows the relationship between the data buffer and peripheral hardware. Figure 10-3. Relationship Between the Data Buffer and Peripheral Hardware
Data buffer (DBF)
Peripheral address Internal bus 01H
Peripheral hardware Shift register (SIOSFR) Timer 0 modulo register (TM0M) Timer 1 modulo register (TM1M) A/D converter data register (ADCR) Address register (AR)
02H
03H Program memory (ROM) 04H Constant data 40H
45H
Timer 0/timer 1 count register (TM0TM1C)
78
CHAPTER 10 DATA BUFFER (DBF)
10.2.1 Data Buffer and Peripheral Hardware Table 10-1 shows data transfer with peripheral hardware using the data buffer. Each unit of peripheral hardware has an individual address (called its peripheral address). By using this peripheral address and the dedicated instructions GET and PUT, data can be transferred between each unit of peripheral hardware and the data buffer. GET DBF, p: Read the data in the peripheral hardware address specified by p into the data buffer (DBF). PUT p, DBF: Write the data in the data buffer to the peripheral hardware address specified by p. There are three types of peripheral hardware units: read/write (PUT/GET), write-only (PUT) and read-only (GET). The following describes what happens when a GET instruction is used with write-only hardware (PUT only) and when a PUT instruction is used with read-only hardware (GET only). * Reading (GET) from write-only (PUT only) peripheral hardware will yield an undefined value. * Writing (PUT) to read-only (GET only) peripheral hardware has no effect (same as a NOP instruction). Table 10-1. Peripheral Hardware (1) Peripheral hardware with input/output in 8-bit units
Peripheral address 01H 02H 03H 04H SIOSFR TM0M TM1M ADCR Serial interface Timer 0 Timer 1 A/D converter x x Name Peripheral hardware Direction of data PUT GET Actual bit length 8 bits 8 bits 8 bits 8 bits
(2) Peripheral hardware with input/output in 16-bit units
Peripheral address 40H 45H AR TM0TM1C Address register Timer 0/timer 1 count register x Name Peripheral hardware Direction of data PUT GET Actual bit length 10/11 bitsNote 16 bits
Note
10 bits for the PD17134A and 17135A, and 11 bits for the PD17136A and 17137A.
79
CHAPTER 10 DATA BUFFER (DBF)
10.2.2 Data Transfer with Peripheral Hardware Data can be transferred between the data buffer and peripheral hardware in 8- or 16-bit units. Instruction execution time for a single PUT or GET instruction is the same regardless of whether 8 or 16 bits are being transferred. Example 1. PUT instruction (when the actual bits in peripheral hardware are the 8 bits from 0 to 7)
Data buffer
DBF3 Don't care
DBF2 Don't care
DBF1
b7 b6 b5 b4 b3
DBF0
b2 b1 b0
PUT Data in peripheral hardware
b7
Actual bits
b0
When only 8 bits of data are being written from the data buffer, the high-order 8 bits (DBF3, DBF2) are "don't care" (any value can be written). 2. GET instruction (when the actual bits in peripheral hardware are the 8 bits from 0 to 7)
Data buffer
DBF3 Retained
DBF2 Retained
DBF1
b7
DBF0
b0
GET Data in peripheral hardware
b7
Actual bits
b0
When 8 bits of data are being read into the data buffer, the values in the high-order 8 bits (DBF3, DBF2) remain unchanged.
80
CHAPTER 10 DATA BUFFER (DBF)
10.2.3 Table Reference By using the MOVT instruction, constant data in program memory (ROM) can be read into the data buffer. The MOVT instruction is explained below. MOVT DBF, @AR: The contents of the program memory being specified by the address register (AR) is read into the data buffer (DBF).
Data buffer DBF3 DBF2 DBF1 DBF0
Program memory (ROM) MOVT DBF, @AR
16 bits b15 b0
81
[MEMO]
82
CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU)
The ALU is used for performing arithmetic operations, logical operations, bit judgements, comparison judgements, and rotations on 4-bit data. 11.1 ALU BLOCK CONFIGURATION Figure 11-1 shows the configuration of the ALU block. As shown in Figure 11-1, the ALU block consists of the main 4-bit data processor, temporary registers A and B which are peripheral circuit of the ALU, the status flip-flop for controlling the status of the ALU, and the decimal correction circuit for use during arithmetic operations in BCD. As shown in Figure 11-1, the status flip-flop consists of the following flags: Zero flag FF, carry flag FF, compare flag FF, and the BCD flag FF. Each flag in the status flip-flop corresponds directly to a flag in the program status word (PSWORD: addresses 7EH, 7FH) in the system register. The flags in the program status word are the following: Zero flag (Z), carry flag (CY), compare flag (CMP), and the BCD flag (BCD). 11.2 FUNCTIONS OF THE ALU BLOCK Arithmetic operations, logical operations, bit judgements, comparison judgements, and rotations are performed using the instructions in the ALU block. Table 11-1 lists each arithmetic/logical instruction, judgement instruction, and rotation instruction. By using the instructions listed in Table 11-1, 4-bit arithmetic/logical operations, judgements and rotations can be performed in a single instruction. Arithmetic operations in decimal can also be performed in a single instruction. 11.2.1 Functions of the ALU The arithmetic operations consist of addition and subtraction. Arithmetic operations can be performed on the contents of the general register and data memory or on immediate data and the contents of data memory. Operations in binary are performed on 4 bits of data and operations in decimal are performed on one place (BCD operation). Logical operations include ANDing, ORing, and XORing. Their operands can be general register contents and data memory contents, or data memory contents and immediate data. Bit judgement is used to determine whether bits in 4-bit data in data memory are 0 or 1. Comparison judgement is used to compare contents of data memory with immediate data. It is used to determine whether one value is equal to or greater than the other, less than the other, or if both values are equal or not equal. Rotation is used to shift 4-bit data in the general register one bit in the direction of its least significant bit (rotation to the right).
83
CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU)
Figure 11-1. ALU Configuration
Data bus
Temporary register A
Temporary register B
Status flip-flop
ALU * Arithmetic operations * Logical operations * Bit judgement * Comparison judgement * Rotations
Decimal correction circuit
Address Name Bit Flag
7EH
7FH Program status word (PSWORD)
b0 BCD
b3 CMP
b2 CY
b1 Z
b0 IXE
Status flip-flop BCD flag FF CMP flag FF CY flag FF Z flag FF
Function outline Indicates when the result of an arithmetic operation is 0. Stores the borrow or carry from an arithmetic operation. Used to indicate whether to store the result of an arithmetic operation. Used to indicate whether to perform decimal correction for arithmetic operations.
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[MEMO]
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Table 11-1. List of ALU Instructions (1/2)
ALU function Arithmetic operations Addition Instruction ADD r, m Operation (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY Explanation Adds contents of general register and data memory. Result is stored in general register. Adds immediate data to contents of data memory. Result is stored in data memory. Adds contents of general register, data memory and carry flag. Result is stored in general register. Adds immediate data, contents of data memory and carry flag. Result is stored in data memory. Subtracts contents of data memory from contents of general register. Result is stored in general register. Subtracts immediate data from data memory. Result is stored in data memory. Subtracts contents of data memory and carry flag from contents of general register. Result is stored in general register. Subtracts immediate data and carry flag from data memory. Result is stored in data memory. (r) (r) v (m) (m) (m) v n4 (r) (r) (m) OR operation is performed on contents of general register and data memory. Result is stored in general register. OR operation is performed on immediate data and contents of data memory. Result is stored in data memory. AND operation is performed on contents of general register and data memory. Result is stored in general register. AND m, #n4 v (m) (m) n4 AND operation is performed on immediate data and contents of data memory. Result is stored in data memory. XOR operation is performed on contents of general register and data memory. Result is stored in general register. XOR operation is performed on immediate data and contents of data memory. Result is stored in data memory. v Skips next instruction if all bits in data memory specified by n are TRUE (1). Result is not stored. Skips next instruction if all bits in data memory specified by n are FALSE (0). Result is not stored. Skips next instruction if immediate data equals contents of data memory. Result is not stored. Skips next instruction if immediate data is not equal to contents of data memory. Result is not stored. Skips next instruction if contents of data memory is greater than or equal to immediate data. Result is not stored. Skips next instruction if contents of data memory is less than immediate data. Result is not stored. Rotate contents of the general register along with the CY flag to the right. Result is stored in general register.
ADD m, #n4
ADDC r, m
ADDC m, #n4 Subtraction SUB r, m
SUB m, #n4
SUBC r, m
SUBC m, #n4 Logical operations Logical OR OR r, m
(m) (m) - n4 - CY
OR m, #n4
AND
Logical XOR
XOR r, m
(r) (r) v (m) (m) (m) v n4 CMP 0, if (m) n=n, then skip CMP 0, if (m) n=0, then skip (m) - n4, skip if zero v
XOR m, #n4
Bit True Judgement False
SKT m, #n
SKF m, #n
Comparison Equal judgement Not equal <
SKE m, #n4
SKNE m, #n4 SKGE m, #n4 SKLT m, #n4 RORC r
(m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow CY(r)b3(r)b2(r)b1(r)b0
Rotation
Rotate to the right
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v
Logical
AND r, m
CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU)
Table 11-1. List of ALU Instructions (2/2)
ALU Function Arithmetic operation Difference in operation because of program status word (PSWORD)
Value of BCD flag 0
Value of CMP flag 0
Operation
CY flag
Z flag
Modification when IXE = 1
Binary operation. Result is stored.
Set when carry or borrow occurs; otherwise, reset
Set if operation result is 0000B; otherwise, reset Retains status if operation result is 0000B; otherwise, reset Set if operation result is 0000B; otherwise, reset Retains status if operation result is 0000B; otherwise, reset
Executed
0
1
Binary operation. Result is not stored.
1
0
BCD operation. Result is stored.
1
- - -- - - - - - - - - - - - - - -- - - - - - - - - - - -
1
- - -- - - - - - - - - - - -
BCD operation. Result is not stored.
- - -- - - - - - - - - - - - - - -- - - - - - - - - - - -
- - -- - - - - - - - - - - -
- - -- - - - - - - - - - - -
Logical operation
Dont'care (retained)
- - -- - - - - - - - - - - --- - -- - - - - - - - - - - -- - - - - - - - - - - --- - -- - - - - - - - -
Don't care (retained)
- - -- - - - - - - - - - - --- - -- - - - - - - - -
Not affected
- - -- - - - - - - - - - - --- - -- - - - - - - - -
Don't care (retained)
- - -- - - - - - - - - - - --- - -- - - - - - - - -
Don't care (retained)
- - -- - - - - - - - - - - --- - -- - - - - - - - -
Executed
- - -- - - - - - - - - - - --- - -- - - - - - - - -
Bit judgement
Dont'care (retained)
------ ------
Reset
------
Not affected
------
Don't care (retained)
------
Don't care (retained)
------
Executed
------
Comparison
Dont'care (retained)
- - -- - - - - - - - - - -- - - - - -- - - - - - - - - - -- - -
Don't care (retained)
- - -- - - - - - - - - - -- - -
Not affected
- - -- - - - - - - - - - -- - -
Don't care (retained)
- - -- - - - - - - - - - -- - -
Don't care (retained)
- - -- - - - - - - - - - -- - -
Executed
- - -- - - - - - - - - - -- - -
Rotation
Dont'care (retained)
Don't care (retained)
Not affected
Value of b0 of general register
Don't care (retained)
Executed
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11.2.2 Functions of Temporary Registers A and B Temporary registers A and B are needed for processing of 4-bit data at a time. These registers are used for temporary storage of the first and second data operands of an instruction. 11.2.3 Functions of the Status Flip-flop The status flip-flop is used for controlling operation of the ALU and for storing data which has been processed. Each flag in the status flip-flop corresponds directly to a flag in the program status word (PSWORD) located in the system register. This means that when a flag in the system register is manipulated it is the same as manipulating a flag in the status flip-flop. Each flag in the program status word is described below. (1) Z flag This flag is set (1) when the result of an arithmetic operation is 0000B, otherwise it is reset (0). However, depending on the status of the CMP flag, the conditions which cause this flag to be set (1) can be changed. (i) When CMP = 0 Z flag is set (1) when the result of an arithmetic operation is 0000B, otherwise it is reset (0). (ii) When CMP = 1 The previous state is maintained when the result of an arithmetic operation is 0000B, otherwise it is reset (0). Only affected by arithmetic operations. (2) CY flag This flag is set (1) when a carry or borrow is generated as a result of an arithmetic operation, otherwise it is reset (0). When an arithmetic operation is being performed using a carry or borrow, the operation is performed using the CY flag as the least significant bit. When a rotation (RORC instruction) is performed, the contents of the CY flag becomes the most significant bit (b3) of the general register and the least significant bit of the general register is stored in the CY flag. Only affected by arithmetic operations and rotations. (3) CMP flag When the CMP flag is set (1), the result of an arithmetic operation is not stored in either the general register or data memory. When the bit evaluation instruction is performed, the CMP flag is reset (0). The CMP flag does not affect comparison judgements, logical operations, or rotations. (4) BCD flag When the BCD flag is set (1), decimal correction is performed for all arithmetic operations. When the flag is reset (0), 4-bit binary operation is performed. The BCD flag does not affect logical operations, bit judgements, comparison judgements, or rotations. These flags can also be set through direct manipulation of the values in the program status word. At this time, the corresponding flag in the status flip-flop is also manipulated.
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11.2.4 Operations in 4-Bit Binary When the BCD flag is set to 0, arithmetic operations are performed in 4-bit binary. 11.2.5 Operations in BCD When the BCD flag is set to 1, decimal correction is performed for arithmetic operations performed in 4-bit binary. Table 11-2 shows the differences in the results of operations performed in 4-bit binary and in BCD. When the result of an addition after decimal correction is equal to or greater than 20, or the result of a subtraction after decimal correction is outside of the range -10 to +9, a value of 1010B (0AH) or higher is stored as the result (shaded area in Table 11-2). Table 11-2. Results of Arithmetic Operations Performed in 4-Bit Binary and BCD
Addition in 4bit binary CY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Addition in BCD CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1110 1111 1100 1101 1110 1111 1100 1101 1010 1011 1100 1101 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 Subtraction in 4-bit binary CY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Subtraction in BCD CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 1110 1111 1100 1101 1110 1111 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Operation result 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Operation
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11.2.6 Operations in the ALU Block When arithmetic operations, logical operations, bit judgements, comparison judgements or rotations in a program are executed, the first data operand is stored in temporary register A and the second data operand is stored in temporary register B. The first data operand is 4-bit data used to specify the contents of an address in the general register or data memory. The second data operand is 4-bit data used to either specify the contents of an address in data memory or to be used as an immediate value. For example, in the instruction ADD r, m Second operand First operand the first operand, r, is used to specify the contents of an address in the general register. The second operand, m, is used to specify the contents of an address in data memory. In the instruction ADD m, #n4 the first operand, m, is used to specify an address in data memory. The second operand, #n4, is immediate data. In the rotation instruction RORC r only the first operand, r (used to specify the contents of an address in the general register) is used. Next, using the data stored in temporary registers A and B, the ALU executes the operation specified by the instruction (arithmetic operation, logical operation, bit judgement, comparison judgement, or rotation). When the instruction being executed is an arithmetic operation, logical operation, or rotation, the data processed by the ALU is stored in the location specified by the first operand (general register address or data memory address) and the operation terminates. When the instruction being executed is a bit judgement or comparison judgement, the result processed by the ALU is used to determine whether or not to skip the next instruction (whether to treat next instruction as a NOP instruction) and the operation terminates. Caution should be taken with regard to the following points: (1) Arithmetic operations are affected by the CMP and BCD flags in the program status word. (2) Logical operations are not affected by the CMP or BCD flag in the program status word. Logical operations do not affect the Z or CY flags. (3) Bit judgement causes the CMP flag in the program status word to be reset. (4) When an arithmetic operation, logical operation, bit judgement, comparison judgement, or rotation is being executed and the IXE flag in the program status word is set (1), address modification is performed using the index register.
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11.3 ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD) As shown in Table 11-3, arithmetic operations consist of addition, subtraction, addition with carry, and subtraction with borrow. These instructions are ADD, ADDC, SUB, and SUBC. The ADD, ADDC, SUB, and SUBC instructions are further divided into addition and subtraction of the general register and data memory and addition and subtraction of data memory and immediate data. When the operands r and m are used, addition or subtraction is performed using the general register and data memory. When the operands m and #n4 are used, addition or subtraction is performed using data memory and immediate data. Arithmetic operations are affected by the status flip-flop and the program status word (PSWORD) in the system register. The BCD flag in the program status word is used to specify whether arithmetic operations are to be performed in 4-bit binary or in BCD. The CMP flag is used to specify whether or not the results of arithmetic operations are to be stored. 11.3.1 to 11.3.4 explain the relationship between each command and the program status word. Table 11-3. Types of Arithmetic Operations
Addition
Arithmetic operation
Without carry ADD
General register and data memory Data memory and immediate data
ADD r, m ADD m, #n4 ADDC r, m ADDC m, #n4 SUB r, m SUB m, #n4 SUBC r, m SUBC m, #n4
With carry ADDC
General register and data memory Data memory and immediate data
Subtraction
Without borrow SUB
General register and data memory Data memory and immediate data
With borrow SUBC
General register and data memory Data memory and immediate data
11.3.1 Addition and Subtraction When CMP = 0 and BCD = 0 Addition and subtraction are performed in 4-bit binary and the result is stored in the general register or data memory. When the result of the operation is greater than 1111B (carry generated) or less than 0000B (borrow generated), the CY flag is set (1); otherwise it is reset (0). When the result of the operation is 0000B, the Z flag is set (1) regardless of whether there is carry or borrow; otherwise it is reset (0). 11.3.2 Addition and Subtraction When CMP = 1 and BCD = 0 Addition and subtraction are performed in 4-bit binary. However, because the CMP flag is set (1), the result of the operation is not stored in either the general register or data memory. When there is a carry or borrow in the result of the operation, the CY flag is set (1); otherwise it is reset (0). When the result of the operation is 0000B, the previous state of the Z flag is retained; otherwise it is reset (0).
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11.3.3 Addition and Subtraction When CMP = 0 and BCD = 1 BCD operations are performed. The result of the operation is stored in the general register or data memory. When the result of the operation is greater than 1001B (9D) or less than 0000B (0D), the carry flag is set (1), otherwise it is reset (0). When the result of the operation is 0000B (0D), the Z flag is set (1), otherwise it is reset (0). Operations in BCD are performed by first computing the result in binary and then by using the decimal correction circuit to convert the result to decimal. For information concerning the binary to decimal conversion, see Table 11-2. In order for operations in BCD to be performed properly, note the following: (1) Result of an addition must be in the range 0D to 19D. (2) Result of a subtraction must be in the range 0D to 9D, or in the range -10D to -1D. The following shows which value is considered the CY flag in the range 0D to 19D (shown in 4-bit binary): 0, 0000B to 1, 0011B CY CY The following shows which value is considered the CY flag in the range -10D to -1D (shown in 4-bit binary): 1, 0110B to 1, 1111B CY CY
When operations in BCD are performed outside of the limits of (1) and (2) stated above, the CY flag is set (1) and the result of operation is output as a value greater than or equal to 1010B (0AH). 11.3.4 Addition and Subtraction When CMP = 1 and BCD = 1 BCD operations are performed. The result is not stored in either the general register or data memory. In other words, the operations specified by CMP = 1 and BCD = 1 are both performed at the same time. Example MOV MOV SUB SUBC SUBC RPL, PSW, M1, M2, M3, #0001B #1010B #0001B #0010B #0011B ; Sets the BCD flag (BCD = 1). ; Sets the CMP and Z flag (CMP = 1, Z = 1) and resets the CY flag ; (CY = 0). ; (1) ; (2) ; (3)
By executing the instructions in steps numbered (1), (2), and (3), the 12 bits in memory locations M1, M2, and M3 and the immediate data (321) can be compared in decimal. 11.3.5 Notes Concerning Use of Arithmetic Operations When performing arithmetic operations with the program status word (PSWORD), caution should be taken with regard to the result of the operation being stored in the program status word. Normally, the CY and Z flags in the program status word are set (1) or reset (0) according to the result of the arithmetic operation being executed. However, when an arithmetic operation is performed on the program status word itself, the result is stored in the program status word. This means that there is no way to determine if there is a carry or borrow in the result of the operation nor if the result of the operation is zero. However, when the CMP flag is set (1), results of arithmetic operations are not stored. Therefore, even in the above case, the CY and Z flags will be properly set (1) or reset (0) according to the result of the operation.
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11.4 LOGICAL OPERATIONS As shown in Table 11-4, logical operations consist of logical OR, logical AND, and logical XOR. Accordingly, the logical operation instructions are OR, AND, and XOR. The OR, AND, and XOR instructions can be performed on either the general register and data memory, or on data memory and immediate data. The operands of these instructions are specified in the same way as for arithmetic operations ("r, m" or "m, #n4"). Logical operations are not affected by the BCD or CMP flags in the program status word (PSWORD). Logical operations do not cause either the CY or Z flag in the program status word (PSWORD) to be set. However, when the index enable flag (IXE) is set (1), index modification is performed using the index register. Table 11-4. Logical Operations
General register and data memory Data memory and immediate data Logical AND General register and data memory Data memory and immediate data Logical XOR General register and data memory Data memory and immediate data OR r, m OR m, #n4 AND r, m AND m, #n4 XOR r, m XOR m, #n4
Logical operation
Logical OR
Table 11-5. Table of True Values for Logical Operations
Logical AND C = A AND B A 0 0 1 1 B 0 1 0 1 C 0 0 0 1 A 0 0 1 1
Logical OR C = A OR B B 0 1 0 1 C 0 1 1 1
Logical XOR C = A XOR B A 0 0 1 1 B 0 1 0 1 C 0 1 1 0
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CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU)
11.5 BIT JUDGEMENTS As shown in Table 11-6, there are both TRUE (1) and FALSE (0) bit judgement instructions. The TRUE (1) and FALSE (0) bit judgements use SKT and SKF instruction, respectively The SKT and SKF instructions can only be used with data memory. Bit judgements are not affected by the BCD flag in the program status word (PSWORD) and bit judgements do not cause either the CY or Z flag in the program status word (PSWORD) to be set. However, when an SKT or SKF instruction is executed, the CMP flag is reset (0). When the index enable flag (IXE) is set (1), index modification is performed using the index register. For information concerning index modification using the index register, see CHAPTER 7 SYSTEM REGISTER (SYSREG). 11.5.1 and 11.5.2 explain TRUE (1) and FALSE (0) bit judgements. Table 11-6. Bit Judgement Instructions
Bit judgement TRUE (1) bit judgement SKT m, #n FALSE (0) bit judgement SKF m, #n
11.5.1 TRUE (1) Bit Judgement The TRUE (1) bit judgement instruction (SKT m, #n) is used to determine whether or not the bits specified by n in the 4 bits of data memory m are TRUE (1). When all bits specified by n are TRUE (1), this instruction causes the next instruction to be skipped. Example MOV SKT BR BR SKT BR BR M1, M1, A B M1, C D #1101B ; (2) #1011B #1011B ; (1)
In this example, bits 3, 1, and 0 of data memory M1 are judged in step number (1). Because all the bits are TRUE (1), the program branches to B. In step number (2), bits 3, 2, and 0 of data memory M1 are judged. Since bit 2 of data memory M1 is FALSE (0), the program branches to C.
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11.5.2 FALSE (0) Bit Judgement The FALSE (0) bit judgement instruction (SKF m, #n) is used to determine whether or not the bits specified by n in the 4 bits of data memory m are FALSE (0). When all bits specified by n are FALSE (0), this instruction causes the next instruction to be skipped. Example MOV SKF BR BR SKF BR BR M1, M1, A B M1, C D #1110B #1001B #0110B ; ; (1) ; ; ; (2) ; ;
In this example, bits 2 and 1 of data memory M1 are judged in step number (1). Because both bits are FALSE (0), the program branches to B. In step number (2), bits 3, 2, and 1 of data memory M1 are judged. Since bit 3 of data memory M1 is TRUE (1), the program branches to C.
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11.6 COMPARISON JUDGEMENTS As shown in Table 11-7, there are comparison judgement instructions for determining if one value is "equal to", "not equal to", "greater than or equal to", or "less than" another. The SKE instruction is used to determine if two values are equal. The SKNE instruction is used to determine two values are not equal. The SKGE instruction is used to determine if one value is greater than or equal to another and the SKLT instruction is used to determine if one value is less than another. The SKE, SKNE, SKGE, and SKLT instructions perform comparisons between a value in data memory and immediate data. In order to compare values in the general register and data memory, a subtraction instruction is performed according to the values in the CMP and Z flags in the program status word (PSWORD). For more information concerning comparison of the general register and data memory, see 11.3 ARITHMETIC OPERATIONS. Comparison judgements are not affected by the BCD or CMP flags in the program status word (PSWORD) and comparison judgements do not cause either the CY or Z flags in the program status word (PSWORD) to be set. 11.6.1 to 11.6.4 explain the "equal to", "not equal to", "greater than or equal to", and "less than" comparison evaluations. Table 11-7. Comparison Judgement Instructions
Comparison judgement Equal to SKE m, #n4 Not equal to SKNE m, #n4 Greater than or equal to SKGE m, #n4 Less than SKLT m, #n4
11.6.1 "Equal to" Judgement The "equal to" judgement instruction (SKE m, #n4) is used to determine if immediate data and the contents of a location in data memory are equal. This instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are equal. Example MOV SKE BR BR ; SKE BR BR M1, C D #1000B ; (2) M1, M1, A B #1010B #1010B ; (1)
In this example, because the contents of data memory M1 and immediate data 1010B in step number (1) are equal, the program branches to B. In step number (2), because the contents of data memory M1 and immediate data 1000B are not equal, the program branches to C.
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11.6.2 "Not Equal to" Judgement The "not equal to" judgement instruction (SKNE m, #n4) is used to determine if immediate data and the contents of a location in data memory are not equal. This instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are not equal. Example MOV SKNE BR BR ; SKNE BR BR M1, C D #1010B ; (2) M1, M1, A B #1010B #1000B ; (1)
In this example, because the contents of data memory M1 and immediate data 1000B in step number (1) are not equal, the program branches to B. In step number (2), because the contents of data memory M1 and immediate data 1010B are equal, the program branches to C. 11.6.3 "Greater Than or Equal to" Judgement The "greater than or equal to" judgement instruction (SKGE m, #n4) is used to determine if the contents of a location in data memory is a value greater than or equal to the value of the immediate data operand. If the value in data memory is greater than or equal to that of the immediate data, this instruction causes the next instruction to be skipped. Example MOV SKGE BR BR ; SKGE BR BR ; SKGE BR BR M1, E F #1001B ; (3) M1, C D #1000B ; (2) M1, M1, A B #1000B #0111B ; (1)
In this example, the program will first branch to B since the value in data memory is larger than that of the immediate data. Next it will branch to D since the value in data memory is equal to that of the immediate data. Last it will branch to E since the value in data memory is less than that of the immediate data.
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11.6.4 "Less Than" Judgement The "less than" judement instruction (SKLT m, #n4) is used to determine if the contents of a location in data memory is a value less than that of the immediate data operand. If the value in data memory is less than that of the immediate data, this instruction causes the next instruction to be skipped. Example MOV SKLT BR BR ; SKLT BR BR ; SKLT BR BR M1, E F #0111B ; (3) M1, C D #1000B ; (2) M1, M1, A B #1000B #1001B ; (1)
In this example, the program will first branch to B since the value in data memory is less than that of the immediate data. Next it will branch to C since the value in data memory is equal to that of the immediate data. Last it will branch to E since the value in data memory is greater than that of the immediate data.
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11.7 ROTATIONS There are rotation instructions for rotation to the right and for rotation to the left. The RORC instruction is used for rotation to the right. The RORC instruction can only be used with the general register. Rotation using the RORC instruction is not affected by the BCD or CMP flags in the program status word (PSWORD) and does not affect the Z flag in the program status word (PSWORD). Rotation to the left is performed by using the addition instruction ADDC. 11.7.1 and 11.7.2 explain rotation. 11.7.1 Rotation to the Right The instruction used for rotation to the right (RORC r) rotates the contents of the general register in the direction of its least significant bit. When this instruction is executed, the contents of the CY flag becomes the most significant bit of the general register (bit 3) and the least significant bit of the general register is placed in the CY flag. Example 1. MOV MOV RORC PSW, R1, R1 #0100B #1001B ; Sets CY flag to 1.
When these instructions are executed, the following operation is performed.
CY flag 1 b3 1 b2 1 b1 0 b0 0
Basically, when rotation to the right is performed, the following operation is executed: CY flag b3, b3 b2, b2 b1, b1 b0, b CY flag. 2. MOV MOV MOV MOV RORC RORC RORC PSW, R1, R2, R3, R1 R2 R3 #0000B #1000B #0100B #0010B ; LSB ; Resets CY flag to 0. ; MSB
The program code above rotates the 13 bits in R1, R2, and R3 to the right.
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CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU)
11.7.2 Rotation to the Left Rotation to the left is performed by using the addition instruction, "ADDC r, m". Example MOV MOV MOV MOV ADDC ADDC ADDC SKF OR PSW, R1, R2, R3, R3, R3 R2, R2 R1, R1 CY R3, #0001B #0000B #1000B #0100B #0010B ; LSB ; Resets CY flag to 0. ; MSB
The program code above rotates the 13 bits in R1, R2, and R3 to the left.
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CHAPTER 12 PORTS
12.1 PORT 0A (P0A0, P0A1, P0A2, P0A3) Port 0A is a 4-bit input/output port with an output latch. It is mapped into address 70H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in 4-bit units. Input/output is specified by P0AGIO (bit 0 at address 2CH) in the register file. When P0AGIO is 0, all pins of port 0A are used as input port. If a read instruction is executed for the port register, pin statuses are read. When P0AGIO is 1, all pins of port 0A are used as output port and the contents written in the output latch are output to pins. If a read instruction is executed when pins are output ports, the contents of the output latch, rather than pin statuses, are fetched. Port 0A contains a software-controlled pull-up resistor. P0AGPU (bit 0 at address 0CH) of the register file is used to determine whether port 0A contains the pull-up resistor. When P0AGPU is 1, all 4-bit pins are pulled up. If P0AGPU is 0, the pull-up resistor is not contained. At reset, P0AGIO and P0AGPU are set to 0 and all P0A pins become input ports without a pull-up resistor. The contents of the port output latch are 0. Table 12-1. Writing into and Reading from the Port Register (0.70H)
BANK0 70H Write Input Output Possible Write to the P0A latch Read P0A pin status P0A latch contents
P0AGIO RF: 2CH, bit 0 0 1
Pin input/output
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12.2 PORT 0B (P0B0, P0B1, P0B2, P0B3) Port 0B is a 4-bit input/output port with an output latch. It is mapped into address 71H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in 4-bit units. Input/ output is specified by P0BGIO (bit 1 at address 2CH) in the register file. When P0BGIO is 0, all pins of port 0B are used as input ports. If a read instruction is executed for the port register, pin statuses are read. When P0BGIO is 1, all pins of port 0B are used as output ports. The contents written in the output latch are output to pins. If a read instruction is executed when pins are used as output ports, the contents of the output latch, rather than pin statuses, are fetched. Port 0B contains a software-controlled pull-up resistor. P0BGPU (bit 1 at address 0CH) is used to determine whether or not port 0B contains a pull-up resistor. When P0BGPU is 1, all 4-bit pins are pulled up. When P0BGPU is 0, a pull-up resistor is not contained. At reset, P0BGIO and P0BGPU are 0 and all P0B pins are input ports without a pull-up resistor. The value of the port 0B output latch is 0. Table 12-2. Writing into and Reading from the Port Register (0.71H)
BANK0 71H Write Input Output Possible Write to the P0B latch Read P0B pin status P0B latch contents
P0BGIO RF: 2CH, bit 1 0 1
Pin input/output
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12.3 PORT 0C (P0C0/ADC0, P0C1/ADC1, P0C2/ADC2, P0C3/ADC3) Port 0C is a 4-bit input/output port with an output latch. It is mapped into address 72H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in 1-bit unit. Input/output can be specified by P0CBIO0 to P0CBIO3 (address 1CH) in the register file. If P0CBIOn is 0 (n = 0 to 3), the P0Cn pins are used as input port. If a data read instruction is executed for the port register, the pin statuses are read. If P0CBIOn is 1 (n = 0 to 3), the P0Cn pins are used as output port and the contents written in the output latch are output to pins. If a read instruction is executed when pins are used as output ports, the contents of the latch, rather than pin statuses, are fetched. At reset, P0CBIO0 to P0CBIO3 are 0 and all P0C pins are input ports. The contents of the port output latch are 0. Port 0C can also be used as an analog input to the A/D converter. P0C0IDI to P0C3IDI (1BH address) in the register file are used to switch the port and analog input pin. If P0CnIDI is 0 (n = 0 to 3), the P0Cn/ADCn pin functions as a port. If P0CnIDI is 1 (n = 0 to 3), the P0Cn/ADCn pin functions as the analog input pin of the A/D converter. ADCCH0 and ADCCH1 (bits 1 and 0 at address 22H) in the register file are used to select the input pin for A/D conversion. To use P0C pins as A/D converter input pins, set P0CBIOn = 0 so that they are set as input ports. (See 13.3 A/D CONVERTER.) At reset, P0CBIO0 to P0CBIO3, P0C0IDI to P0C3IDI, ADCCH0, and ADCCH1 are set to 0 and the P0C pins are used as input ports. Table 12-3. Switching the Port and A/D Converter
(n = 0 to 3) P0CnIDI RF: 1BH 0 P0CBIOn RF: 1CH 0 Input port Function Write Possible P0C latch Possible P0C latch Possible P0C latch Possible P0C latch BANK0 72H Read Pin status
1
Port output
P0C latch contents
1
0
A/D converter analog inputNote1 Output port and A/D converter analog inputNote2
P0C latch contents
1
P0C latch contents
Notes 1. 2.
Normal setting when the pins are used as A/D converter analog input pins. Functions as an output port. At this time, the analog input voltage changes affected by the port output. When using this pin as an analog input pin, be sure to set P0CBIOn to 0.
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12.4 PORT 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TM0OUT) Port 0D is a 4-bit input/output port with an output latch. It is mapped into address 73H of BANK0 in data memory. The output format is N-ch open-drain output. The mask option can be used to specify that a pin contain a pull-up resistor in 1-bit unit. Input or output can be specified in 1-bit unit. Input/output is specified with P0DBIO0 to P0DBIO3 (address 2BH) in the register file. If P0DBIOn is 0 (n = 0 to 3), the P0Dn pins are used as input port. Pin statuses are read if a data read instruction is executed for the port register. If P0DBIOn is 1, the P0Dn pins are used as output port and the value written in the output latch are output to pins. If a data read instruction is executed when pins are used as output ports, the output latch value, rather than pin statuses, is fetched. At reset, P0DBIOn is set to 0 and all P0D pins become input ports. The contents of the port output latch become 0. The output latch contents remain unchanged even if P0DBIOn changes from 1 to 0. Port 0D can also be used for serial interface input/output or timer 0 output. SIOEN (0BH bit 0) in the register file is used to switch ports (P0D0 to P0D2) to serial interface input/output (SCK, SO, SI) and vice versa. TM0OSEL (bit 3 at address 0BH) in the register file is used to switch a port (P0D3) to timer 0 output (TM0OUT) and vice versa. If TM0OSEL = 1 is selected, 1 is output at timer 0 reset. This output is inverted every time a timer 0 count value matches the modulo register contents. Table 12-4. Register File Contents and Pin Functions
(n = 0 to 3) Register file value TM0OSEL RF: 0BH Bit 3 SIOEN RF: 0BH Bit 0 0 0 0 1 1 0 0 1 0 1 1 SCK SO SI 1 Input port Output port TM0OUT SCK Input port SO SI Output port P0DBIOn RF: 2BH Bit n 0 1 Pin function
P0D0/SCK
P0D1/SO
P0D2/SI
P0D3/TM0OUT
Input port Output port
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Table 12-5. Contents Read from the Port Register (0.73H)
Port mode Input port Output port An internal clock is selected as a shift clock. SCK An external clock is selected as a shift clock. SI SO TM0OUT
Contents read from the port register (0.73H) Pin status Output latch contents Output latch contents Pin status Pin status Not defined Output latch contents
Caution Using the serial interface causes the output latch for the P0D1/SO pin to be affected by the contents of the SIOSFR (shift register). So, reset the output latch before using the pin as output port. 12.5 PORT 1A (P1A0, P1A1, P1A2, P1A3) Port 1A is a 4-bit input/output port with an output latch. It is mapped into address 70H of BANK1 in data memory. The output format is N-ch open-drain output. The mask option can be used to specify that a pin contain a pull-up resistor in 1-bit unit. Input or output can be specified in 4-bit units. Input/output is specified by P1AGIO (bit 2 at address 2CH) in the register file. When P1AGIO is 0, each pin of port 1A is used as input port. If a read instruction is executed for the port register, pin statuses are read. When P1AGIO is 1, each pin of port 1A is used as output port and the contents written in the output latch are output to pins. If a read instruction is executed when pins are output ports, the contents of the output latch, rather than pin statuses, are fetched. At reset, P1AGIO is set to 0 and all P1A pins become input ports. The contents of the port output latch are 0. Table 12-6. Writing into and Reading from the Port Register (1.70H)
(n = 0 to 3) P1AGIOn RF: 2CH, bit 2 0 1 BANK1 70H Pin input/output Write Input Output Possible Write to the P1A latch Read P1A pin status P1A latch contents
12.6 PORT 1B (P1B0) Port 1B is a 1-bit input-dedicated port. It is mapped into address 71H of BANK1 in data memory. The mask option can be used to specify that pull-up resistors be contained in P1B0 pins. Port 1B is the input-dedicated port. At reading, only the least significant bit is valid and a value is read into it. At writing, no value changes. Value 0 is always read into the high-order 3 bits of the port register.
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12.7 PORT CONTROL REGISTER 12.7.1 Input/Output Switching by Group I/O Ports which switch input/output in 4-bit unit are called group I/O. Port 0A, port 0B, and port 1A are used as group I/O. The register shown in the figure below is used for input/output switching. Figure 12-1. Input/Output Switching by Group I/O
RF: 2CH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 P1AGIO R/W 0 0 Bit 1 P0BGIO Bit 0 P0AGIO Read = R, write = W
P0AGIO 0 1
Function Sets port 0A to input mode. Sets port 0A to output mode.
P0BGIO 0 1
Function Sets port 0B to input mode. Sets port 0B to output mode.
P1AGIO 0 1
Function Sets port 1A to input mode. Sets port 1A to output mode.
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12.7.2 Input/Output Switching by Bit I/O Ports which switch input/output in 1-bit unit are called bit I/O. Port 0C and port 0D are used as bit I/O. The register shown in the figure below is used for input/output switching. Figure 12-2. Port Control Register of Bit I/O (1/2)
RF: 1CH Bit 3 P0CBIO3 Read/write Initial value when reset 0 0 Bit 2 P0CBIO2 R/W 0 0 Bit 1 P0CBIO1 Bit 0 P0CBIO0 Read = R, write = W
P0CBIO0 0 1
Function Sets P0C0 to input mode. Sets P0C0 to output mode.
P0CBIO1 0 1
Function Sets P0C1 to input mode. Sets P0C1 to output mode.
P0CBIO2 0 1
Function Sets P0C2 to input mode. Sets P0C2 to output mode
P0CBIO3 0 1
Function Sets P0C3 to input mode. Sets P0C3 to output mode.
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Figure 12-2. Port Control Register of Bit I/O (2/2)
RF: 2BH Bit 3 P0DBIO3 Read/write Initial value when reset 0 0 Bit 2 P0DBIO2 R/W 0 0 Bit 1 P0DBIO1 Bit 0 P0DBIO0 Read = R, write = W
P0DBIO0 0 1
Function Sets P0D0 to input mode. Sets P0D0 to output mode.
P0DBIO1 0 1
Function Sets P0D1 to input mode. Sets P0D1 to output mode.
P0DBIO2 0 1
Function Sets P0D2 to input mode. Sets P0D2 to output mode.
P0DBIO3 0 1
Function Sets P0D3 to input mode. Sets P0D3 to output mode.
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12.7.3 Specifying Pull-Up Resistor Incorporation Using Software Pull-up resistor incorporation can be specified in 4-bit units using P0AGPU and P0BGPU (address 0CH) in the register file. Figure 12-3. Specifying Pull-Up Resistor Incorporation Using Software
RF: 0CH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 Bit 1 P0BGPU Bit 0 P0AGPU Read = R, write = W
P0AGPU 0 1
Function Does not contain pull-up resistor in port 0A. Contains pull-up resistor in port 0A.
P0BGPU 0
Function Does not contain pull-up resistor in port 0B. Contains pull-up resistor in port 0B.
1
109
[MEMO]
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CHAPTER 13 PERIPHERAL HARDWARE
13.1 8-BIT TIMERS/COUNTERS (TM0 AND TM1) The PD17134A subseries has two channels of 8-bit timers/counters: timer 0 (TM0) and timer 1 (TM1). These two timers can be used in combination as a 16-bit timer by using the count up signal of timer 0 as the count pulse for timer 1. These timers are controlled by manipulating the hardware with the PUT/GET instruction and registers in the register file with the PEEK/POKE instruction. 13.1.1 8-Bit Timers/Counters Configuration Figure 13-1 shows the configuration of the 8-bit timers/counters. An 8-bit timer/counter consists of an 8-bit count register, 8-bit modulo register, a comparator that compares the value of the count register and the value of the modulo register, and a selector that selects a count pulse. Cautions 1. The modulo register is a write-only register. 2. The count register is a read-only register.
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Figure 13-1. Configuration of the 8-Bit Timer Counters
Data buffer (DBF) Internal bus AC zero cross detection circuit control register (RF : 1DH) ZCROSS Interrupt control register (RF : 0FH) INT Timer 0 mode register (RF : 11H) TM0EN TM0RES TM0CK1 TM0CK0 Timer 0 modulo register (8) (TM0M) Match Timer 0 comparator (8) Latch fX/256 fX/64 fX/16 INT
AC zero cross detection circuit
Serial interface control register (RF : 0BH) TM0OSEL
Bit I/O port control register (RF : 2BH) P0DBIO3
P0DB3 output latch
2
P0D3/ TM0OUT
TM0OUT F/F
Reset D Selector CLK R Reset To basic interval timer Internal reset Q Timer 0 count register (8) (TM0C) Clear IRQTM0 set signal
Timer 0 count up signal (To timer 1 and basic interval timer)
IRQTM0 clear signal
Data buffer (DBF)
Internal bus Timer 1 mode register (RF : 12H) TM1EN TM1RES TM1CK1 TM1CK0
Timer 1 modulo register (8) (TM1M)
Match 2 Timer 1 comparator (8) Latch fX/512 fX/1024 fX/256 Timer 0 count up D Selector Q CLK R Reset
Timer 1 count register (8) (TM1C)
IRQTM1 set signal
Clear
Internal reset IRQTM1 clear signal
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-2. Timer 0 Mode Register
RF : 11H
Bit 3 TM0EN
Bit 2 TM0RES
Bit 1 TM0CK1
Bit 0 TM0CK0 Read = R, Write = W
Read/write Initial value when reset 0 0
R/W 0 0
TM0CK1 0 0 1 1
TM0CK0 0 1 0 1
Selects count pulse of timer 0 fX/256 fX/64 fX/16 External clock from INT pin
TM0RES 0 1
Resets timer 0 Does not affect timer 0 Resets timer 0 count register and IRQTM0
Remark TM0RES is automatically cleared to 0 after it has been set to 1. This bit is always 0 when it is read.
TM0EN 0 1
Starts timer 0 Stops counting by timer 0 Starts counting by timer 0
Remark TM0EN can be used as a status flag that detects the counting status of timer 0 (1: counting in progress, 0: counting is stopped).
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Figure 13-3. Timer 1 Mode Register
RF : 12H
Bit 3 TM1EN
Bit 2 TM1RES
Bit 1 TM1CK1
Bit 0 TM1CK0
Read/write Initial value when reset 1 0
R/W 0 0
TM1CK1 0 0 1 1
TM1CK0 0 1 0 1
Selects count pulse of timer 1 fX/512 fX/1024 fX/256 Count up signal from timer 0
TM1RES 0 1 1
Resets timer 1 Does not affect timer 1 Resets timer 1 count register and IRQTM
Remark TM1RES is automatically cleared to 0 after it has been set to 1. This bit is always 0 when it is read.
TM1EN 0 1
Starts timer 1 Stops counting by timer 1 Starts counting by timer 1
Remark TM1EN can be used as a status flag that detects the counting status of timer 0 (1: counting in progress, 0: counting is stopped).
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13.1.2 Operation of 8-Bit Timers/Counters (1) Count register The count register of timers 0 and 1 is an 8-bit up counter whose initial value is 00H, and is incremented each time a count pulse has been input. The count register is initialized to 00H in the following cases. (1) When this product is reset (refer to CHAPTER 17 RESET). (2) When the contents of the 8-bit modulo register and the value of the count register coincide, and the comparator generates a coincidence signal. (3) In the case of timer 0, when "1" is written to TM0RES of the register file. In the case of timer 1, when "1" is written to TM1RES of the register file. (2) Modulo register The modulo register of timers 0 and 1 determines the count value of the count register and its initial value is set to FFH. A value is set to the modulo register by using the PUT instruction via DBF (data buffer). (3) Comparator The comparator of timers 0 and 1 outputs a coincidence signal when the value of the count register and the value of the modulo register coincide. If the value of the modulo register is the initial value FFH, for example, the comparator outputs the coincidence signal when the count register counts 256. The coincidence signal output from the comparator clears the contents of the count register to 0, and automatically sets interrupt request flags (IRQTM0 and IRQTM1) to "1". If the EI instruction (that enables accepting interrupts) is executed, and if the interrupt enable flags (IPTM0 and IPTM1) are set at this time, interrupts are accepted. When an interrupt has been accepted, the interrupt request flag (IRQTM0 or IRQTM1) is cleared to "0", and program execution branches to a specified interrupt routine. 13.1.3 Selecting Count Pulse The count pulse for timer 0 is selected by TM0CK0 and TM0CK1. As the count pulse, a pulse resulting from dividing the system clock (fX) by 256, 64, or 16, or an external count pulse input from the INT pin can be selected. At reset, fX/256 is selected as a count pulse because TM0CK0 = 0 and TM0CK1 = 0. The count pulse for timer 1 is selected by TM1CK0 and TM1CK1. As the count pulse, a pulse resulting from dividing fX by 1024, 512, or 256, or the count up signal from timer 0 can be selected. Timer 1 is also used to generate oscillation stabilization time on power application or at reset. Therefore, the initial values are TM1CK0 = 0 and TM1CK1 = 0, and fX/512 is selected as the count pulse. Because TM1EN = 1 as the initial condition, the PD17134A subseries starts program execution from address 0000H after it has been reset at fX = 8 MHz and after about 16.4 ms (about 65.5 ms at 2 MHz) (refer to CHAPTER 17 RESET).
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13.1.4 Setting Count Value to Modulo Register A value is set to the modulo register by using the PUT instruction via DBF (data buffer). The peripheral address of the modulo register of timer 0 is assigned to 02H, and that of timer 1 is assigned to 03H. To transfer a value by using the PUT instruction, the data of the low-order 8 bits of DBF (DBF1 and DBF0) are transferred to the modulo register. Figure 13-4 shows an example of the modulo register of timer 0. Figure 13-4. Setting Count Value to Modulo Register Example of setting count value 64H to modulo register of timer 0 CONTDATL CONTDATH DAT DAT MOV MOV PUT 4H 6H ; Assigns CONTDATL to 4H by using symbol definition instruction ; Assigns CONTDATH to 6H by using symbol definition instruction
DBF0, #CONTDATL ; DBF1, #CONTDATH ; TM0M, DBF ; Transfers data by using reserved word "TM0M"
Data buffer DBF3 b3 b2 b1 b0 b3 DBF2 b2 b1 b0 b3 0 DBF1 b2 1 b1 1 b0 0 b3 0 DBF0 b2 1 b1 0 b0 0
Don't care
Don't care
8-bit data PUT TM0M, DBF
TM0M (peripheral address 02H) b7 0 b6 1 b5 1 b4 0 b3 0 b2 1 b1 0 b0 0
Caution The range of the value to that can be set to the modulo register is 01H to FFH. If 00H is set, the normal count operation is not performed. The modulo register is a write-only register. Therefore, the set value of the modulo register cannot be read. Even if the "PUT TM0M, DBF" or "PUT TM1M, DBF" instruction is executed while the 8-bit timer/counter is operating, the count is operating is not stopped.
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13.1.5 Reading Value of Count Register The values of the count registers of timers 0 and 1 are read simultaneously by using the GET instruction via DBF (data buffer). The values of the count registers of timers 0 and 1 are assigned to peripheral address 45H. The high-order 8 bits of this address are assigned to the count value of timer 1, and the low-order 8 bits are assigned to the count value of timer 0. The values of the count registers can be read to DBF by using the GET instruction. While the GET instruction is being executed, the count registers stop counting and hold the current count value. If a count pulse is input to the timer while the timer is operating and the GET instruction is being executed, the count value is held, the value of the count register is incremented by one after the GET instruction has been executed, and the timer continues counting. Therefore, the timer does not count erroneously even if the GET instruction is executed while the timer is operating, unless two or more count pulses are input to the timer in one instruction cycle. Figure 13-5. Reading Count Value of Count Register Example of using GET DBF, TM0TM1C; reserved word DBF and TM0TM1C when count value of timer 0 is F0H and count value of timer 1 is A4H
Data buffer DBF3 b3 1 b2 0 b1 1 b0 0 b3 0 DBF2 b2 1 b1 0 b0 0 b3 1 DBF1 b2 1 b1 1 b0 1 b3 0 DBF0 b2 0 b1 0 b0 0
GET DBF, TM0TM1C 16-bit data TM0TM1C (peripheral address) b15 b14 b13 b12 b11 b10 1 0 1 0 0 1 b9 0 b8 0 b7 1 b6 1 b5 1 b4 1 b3 0 b2 0 b1 0 b0 0
Timer 1 count value
Timer 0 count value
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13.1.6 Setting of Interval Time The time interval at which the comparator outputs the coincidence signal is determined by the value set to the modulo register. The set value N of the modulo register is calculated from interval time T [sec] as follows: N+1 fCP
T=
= (N + 1) x TCP
N = T x fCP - 1 or N =
T TCP
- 1 (where, N = 1 to 255)
fCP
: Frequency of count pulse [Hz]
TCP : Cycle of count pulse [sec] (1/fCP = resolution)
*
Example of calculating count value from interval time and program * Example of setting 7 ms to timer 1 as interval time (system clock: fX = 8 MHz) Suppose one wanted to set the interval timer to 7 ms. It is impossible to set an interval time of exactly 7 ms from an 8-MHz system clock. To set an interval time closest to 7 ms, therefore, calculate the count value by selecting a count pulse (fX/256, resolution: 32 s) at which the resolution is maximum. Example of calculation T (Resolution) 7 x 10-3 32 x 10-6 T = 7 ms, Resolution = 32 s
N=
-1
=
-1
. = 217.75 = 218 (= DAH) . The value of the modulo register at which the interval time is closest to 7 ms is DAH, and the interval time at that time is 7.008 ms. Program example MOV MOV PUT DBF0, DBF1, TMM, #0AH #0DH DBF ; Stores DAH to DBF by using reserved words "DBF0" and "DBF1" ; Storage ; Transfers contents of DBF by using reserved word "TMM"
INITFLG TM1EN, TM1RES, TM1CK1, NOT TM1CK0 ; Sets TM1EN and TM1RES, sets count pulse of timer 1 to "fX/256", and starts ; counting, by using embedded macroinstruction "INITFLG"
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13.1.7 Error of Interval Time The interval time may include an error of up to -1.5 count, especially if the value set value of the modulo register is low. (1) Error when count register is cleared to 0 during counting (maximum error: -1 count) The count register of the 8-bit timer/counter is cleared to 0 when the TMnRES flag is set to 1. However, the divider circuit that generates a count pulse from the system clock is not reset. Therefore, an error of 1 cycle of the count pulse may be generated at the first count if the TMnRES flag is set to 1 and the count value is cleared to 0 during counting. An example of counting where 2 is set to the modulo register is shown below. Figure 13-6. Error When Count Register Is Cleared to 0 During Counting
Count cleared (TMnRES 0) 2 to 3 counts
Count pulse
Count register
1
2
0
1
2
Output of coincidence signal
In this example, the coincidence signal must be output each time the count value has reached 3. However, the coincidence signal is output when the count value reaches 2 for the first time after the count has been cleared. The above error also occurs when TMnRES 1 at the same time as TMnEN = 1 0.
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CHAPTER 13 PERIPHERAL HARDWARE
(2) Error when counting is started from count stop status (maximum error: -1.5 count) The count register of the 8-bit timer is cleared to 0 by setting the TMnRES flag to 1. However, the divider circuit that generates a count pulse from the system clock is not reset. If the TMnEN flag is set to 1 and counting is started from the count stop status, the timing of the first counting differs as follows depending on whether the count pulse starts with a low level or a high level. If count pulse starts with high level: First count at the next rising If count pulse starts with low level: First count on starting of counting Therefore, an error of -0.5 to 1.5 count occurs until the coincidence signal is output for the first time after counting has been started. An example of counting where the modulo register is set to 1 is shown below. Figure 13-7. Error When Counting Is Started from Count Stop Status (a) If counting is started when count pulse is high (error: -0.5 to -1 count)
Count starts (TMnEN = 1 0) 1 to 1.5 count 2 counts
Count pulse
Count register
0
1
0
1
Coincidence signal output
Coincidence signal output
(b) If counting is started when count pulse is low (error: -1 to -1.5 count)
Count starts (TMnEN = 1 0) 0.5 to 1 count 2 counts
Count pulse
Count register
0
1
0
1
0
Coincidence signal output
Coincidence signal output
In this example, the coincidence signal must be output each time the count value has reached 2. However, the first coincidence signal is output when the count value is 1.5 at maximum or 0.5 at minimum (error: -0.5 to -1.5 count). The above error also occurs during oscillation stabilization wait time because the timer is also used to generate the oscillation stabilization wait time.
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13.1.8 Timer 0 Output The POD3/TM0OUT pin functions as timer 0 output pin by setting the TM0OSEL flag to "1". At this time, the value of P0DBIO3 is irrelevant. Timer 0 has an internal flip-flop for outputting a coincidence signal. The output of this flip-flop is inverted each time the comparator has output the coincidence signal. If the TM0OSEL flag is set to "1", the content of this flip-flop is output to the P0D3/TM0OUT pin. The P0D3/TM0OUT pin is an N-ch open-drain output pin and can be connected to a pull-up resistor by mask option. If the pull-up resistor is not connected, the P0D3/TM0OUT pin goes into a high-impedance state as the initial status. The internal timer 0 output flip-flop starts operating as soon as TM0EN has been set to 1. To make sure that timer 0 output always starts from the initial status, set TM0RES to 1 and reset the flip-flop before starting counting. Figure 13-8. Timer 0 Output Setting Register
RF : 0BH
Bit 3 TM0OSEL
Bit 2 0 R/W
Bit 1 0
Bit 0 SIOEN Read = R, write = W
Read/write Initial value when reset 0 0
0
0
SIOEN 0
Function P0D0/SCK, P0D1/SO, and P0D2/SI pins function as port pins. P0D0/SCK, P0D1/SO, and P0D2/SI pins
1 function as serial interface pins. Caution This bit is not directly related to output setting of timer 0. TM0OSEL 0 1 Function P0D3/TM0OUT pin functions as port pin. P0D3/TM0OUT pin outputs coincidence signal of timer 0.
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13.2 BASIC INTERVAL TIMER (BTM) The PD17134A subseries has a 7-bit basic interval timer. This basic interval timer has the following functions. (1) Generates reference time. (2) Selects and counts wait time when standby mode is released. (3) Serves as watchdog timer that detects program hang-up. 13.2.1 Basic Interval Timer Configuration Figure 13-9 shows the configuration of the basic interval timer. Figure 13-9. Basic Interval Timer Configuration
Internal bus BTM mode register (RF: 13H) Watchdog timer mode register (RF: 03H) WDTRES 0 0 WDTEN
BTMISEL BTMRES BTMCK1 BTMCK0
2 Reset fX/8192 fX/4096 Timer 0 count up INT pin (ACZCROSS) fBTM fBTM 26
fBTM
Selector (2)
IRQBTM set signal
Selector
Basic interval timer (7-bit divider circuit)
27
(3)
Watchdog reset signal
Reset 1-bit divider circuit
R
1-shot pulse generation circuit
Q
(4)
(1)
S
Outputs 1 while counting 0 to 7 during count of 0 to 256
Remark (1) through (4) in the figure corresponding to the signals in the timing chart in Figure 13-12.
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CHAPTER 13 PERIPHERAL HARDWARE
13.2.2 Registers Controlling Basic Interval Timer The basic interval timer is controlled by the BTM mode register and watchdog timer mode register. Figures 13-10 and 13-11 show the configuration of the respective registers. Figure 13-10. BTM Mode Register
RF : 13H
Bit 3
Bit 2
Bit 1 BTMCK1
Bit 0 BTMCK0 Read = R, write = W
BTMISEL BTMRES Read/write Initial value when reset 0 0
R/W 0 0
BTMCK1 0
BTMCK0 Selects count pulse of BTM fX/8192 0 (execution time of 512 instructions) fX/4096
0
1 (execution time of 256 instructions)
1
0
Count up of timer 0 INT pin
1
1
(information on INT pin that has gone through AC zero cross detection circuit when ZCROSS = 1)
BTMRES 0 1
Resets BTM Does not affect basic interval timer (BTM). Resets binary counter of basic interval timer (BTM).
Remark BTMRES is automatically cleared to 0 after it has been set to 1. This bit is always "0" when it is read.
BTMISEL 0 time.
Selects interval time Sets count pulse divided by 128 as interval
Sets count pulse divided by 32 as interval 1 time.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-11. Watchdog Timer Mode Register
RF : 03H
Bit 3 WDTRES
Bit 2 0 R/W
Bit 1 0
Bit 0 WDTEN Read = R, write = W
Read/write Initial value at reset 0 0
0
0
WDTEN 0
Enables watchdog timer function Watchdog timer stops.
1
Watchdog timer starts operating.
Remarks 1. WDTEN cannot be cleared to 0 by program. 2. WDTEN is automatically cleared to 0 after it has been set to 1. This bit is always 0 when it is read.
WDTRES 0 1
Resets watchdog timer Does not affect watchdog timer. Sets flip-flop that holds overflow carry of BTM used by watchdog timer.
Remark WDTRES is automatically cleared to 0 after it has been set to 1. This bit is always 0 when it is read.
13.2.3 Operation of Basic Interval Timer The basic interval timer is a 7-bit binary counter that always counts up by using a count pulse specified by the BTM mode register. Counting operation cannot be stopped. The interval time of the basic interval timer can be changed by using the BTMISEL bit of the BTM mode register. When BTMISEL = 0, the interval time is the count pulse divided by 128 (128/fBTM); when BTMISEL = 1, the interval time is the count pulse divided by 32 (32/fBTM). The contents of the counter are not cleared to 0 even if the interval time is changed.
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CHAPTER 13 PERIPHERAL HARDWARE
13.2.4 Watchdog Timer Function The basic interval timer can also be used as a watchdog timer to detect a program hang-up. (1) Function of watchdog timer The watchdog timer is a counter that generates a reset signal at fixed intervals. By inhibiting the generation of this reset signal each time through program, the system can be reset (and started from address 0000H) if it has overrun due to an external noise (i.e., if the watchdog timer is not reset within the time set by program). This function can prevent the system from overrunning even if the program is caused to jump to an unexpected routine by an external noise and enter an infinite loop, because a reset signal is generated at fixed intervals. (2) Operation of the watchdog timer When "1" is set to WDTEN, the 1-bit divider is enabled to operate, and consequently, the basic interval timer operates as an 8-bit watchdog timer. Once the watchdog timer has been started, it cannot be stopped until the device is reset and WDTEN is cleared to 0. Generation of the reset signal by the watchdog timer can be inhibited in the following two ways: (i) Repeat setting WDTRES in program.
(ii) Repeat setting BTMRES in program. In the case of (i), WDTRES must be set while the count value of the watchdog timer is between 8 and 191 (immediately before it reaches 192). Therefore, "SET1 WDTRES" must be executed at least once at a timing shorter than the cycle in which the count value of the watchdog timer reaches 184. In the case of (ii), BTMRES must be set until the count value of the basic interval timer (BTM) reaches 128. Therefore, "SET BTMRES" must be executed at least once at a timing shorter than the cycle in which the count value of BTM reaches 128. In this case, however, interrupt processing cannot be performed by BTM. Caution BTM is not reset even if WDTEN is set. Therefore, be sure to set BTMRES and reset BTM before setting WDTEN first. Example SET1 SET2 . . .
. . . BTMRES WDTEN, WDTRES
125
126
Figure 13-12. Timing Chart of Watchdog Timer (with WDTRES Flag Used)
255 255 192 128 64 8 8 8 0 128 128 192 192 255 192 128 WDTRES accepting period WDTRES accepting period WDTRES accepting period Reset signal is not generated
Count value of watchdog timer
WDTEN
WDTRES
CHAPTER 13 PERIPHERAL HARDWARE
1-shot pulse generator circuit output (1)
(4)
fBTM/27(2)
(fl IRQBTM set)
fBTM/28(3)
Watchdog reset signal (active high)
CHAPTER 13 PERIPHERAL HARDWARE
(3) Program example of watchdog timer Program Example
Start
ORG BR ORG BR
0H INITJOB 2H INTBTMJOB
Initialize
INITJOB: INITFLG SET1 SET2 SET1 CLR1 EI
NOT BTMISEL, BTMRES, NOT BTMCK1, BTMCK0 BTMRES WDTRES, WDTEN; Watchdog timer start IPBTM IRQBTM ; BTM interrupt enable
Main Processing
MAIN: CALL CALL
......
JOB1 JOB2
......
END
JOB1: CLR1 IPBTM
JOB2: CLR2 IPBTM
INTBTMJOB: SET1 WDTRES EI RETI
SET1 BTMRES
SET1 BTMRES
SET1 BTMRES
SET IPBTM RET Reset BTM before its count value reaches to 128Note 1.
.......... .......... .......... ..........
SET1 WDTRES
SET1 WDTRES
SET IPBTM RET Reset watchdog timer before its count value reaches to 184. Reset watchdog timer by using interrupt processing of BTMNote 2.
......................... .......... ..........
Notes 1. 2.
Interrupt processing by BTM cannot be performed in the method to reset counter before BTM overflows. Although the method of resetting the watchdog timer by using the BTM interrupt processing is easier to program than the other two methods, its program hang-up detection rate is lower than that of the other two.
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CHAPTER 13 PERIPHERAL HARDWARE
13.3 A/D CONVERTER
PD17134A subseries contains an 8-bit resolution A/D converter with 4-channel analog input (P0C0/ADC0 - P0C3/
ADC3). The A/D converter uses the successive approximation method. The following two operation modes are available: (1) Successive mode: 8-bit A/D conversion occurs starting at high-order bits. (2) Single mode: Comparison occurs with an arbitrary voltage value set in the 8-bit data register. 13.3.1 A/D Converter Configuration Figure 13-13 shows the A/D converter configuration. Figure 13-13. Block Diagram of the A/D Converter
Remark n = 0 to 3 Internal bus
Read signal P0CnIDI P0CBIOn
RF: 22H
0 0 ADCCH1 ADCCH0
RF: 20H
RF: 21H
ADCSOFT 0 ADCCMP ADCEND
0 0 0 ADCSTRT
Selector
Output latch
Control circuit
8 4 P0Cn/ADCn Selector Comparator 8-bit data register (ADCR)
A/D end signal STOP instruction signal Tap decoder VADC Analog power of A/D converter 3R/2 R R R/2 D/A converter 8
Cautions 1. The 8-bit data register (ADCR) is cleared to 00H when the STOP instruction has been executed. 2. If the HALT instruction is executed during A/D conversion, a current keeps flowing between VADC and GND.
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CHAPTER 13 PERIPHERAL HARDWARE
13.3.2 Functions of A/D Converter (1) ADC0 - ADC3 These pins are used to input 4-channel analog voltage to the A/D converter. The A/D converter contains a sample hold circuit. Analog input voltage is internally retained during A/D conversion. (2) VADC This pin is used to input the power supply and the reference voltage for the A/D converter. A signal input to ADC0 to ADC3 is converted to a digital signal based on voltage applied across VADC and GND. To reduce the current consumption of the microcontroller, the A/D converter has a function for automatically stopping the current which flows into the VADC pin when the converter is not operating. Current flows into the VADC pin in the following cases. <1> Successive mode (ADCSOFT=0) From when the ADCSTRT flag is set (1) until the ADCEND flag is set (1). <2> Single mode (ADCSOFT=1) From when the ADCSTRT flag is set (1) or from when a value of the 8-bit data register is written until the result of comparison by the comparator is written in the ADCCMP flag. Caution If the HALT Instruction is executed while the A/D conversion is in progress, the A/D converter stops conversion. Note that, in this case, the HALT mode is set with current flowing to the VADC pin. When the HALT mode has been released, the A/D conversion is resumed. At this time, however, the value of ADCR is undefined, and the correct conversion result cannot be obtained. Remark A/D conversion is stopped if the STOP instruction is executed while the conversion is in progress. In this case, the A/D converter is initialized, and the current to the VADC pin is also cut. The A/D converter remains stopped even if the STOP mode has been released. (3) 8-bit data register (ADCR) In the successive mode, this 8-bit data register stores A/D conversion results for successive approximation. It is read by the GET instruction. In the single mode, the data in this register is converted to analog voltage by the internal D/A converter and the comparator compares this voltage with an analog signal input from the ADCn pin. A value can be written in this register by using the PUT instruction. (4) Comparator The comparator compares an analog input voltage from a pin with voltage output from the D/A converter. Value 1 is output if analog input voltage from the pin is high. Value 0 is output if this voltage is low. The comparison result is stored in the 8-bit data register (ADCR) in the successive mode. It is stored in the ADCCMP flag in the single mode. (5) A/D converter control register Figure 13-14 shows the A/D converter control register.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-14. A/D Converter Control Register (1/2)
RF: 21H Bit 3 ADCSOFT Read/write Initial value when reset 0 R/W 0 0 Bit 2 0 Bit 1 Bit 0 ADCCMP ADCEND R 0 Read = R, write = W
ADCEND 0
End of A/D conversion Initial status or during A/D conversion. Indicates the end of A/D conversion in
1
successive mode. Cleared to 0 by setting (1) or resetting ADCSTRT.
ADCCMP Compare result (valid only in the single mode) 0 Analog input voltage is lower than output voltage of the internal D/A converter. Analog input voltage is higher than output voltage of the internal D/A converter.
1
Remarks 1.
In the single mode, the flag content is valid for the third and subsequent instructions after ADCSTRT is set (1) or data is set in ADCR until ADCSTRT or ADCR is set again.
2.
In the successive mode, a value changes according to an A/D conversion value. However, the bit for this value cannot be identified.
3.
ADCCMP is automatically cleared to 0 when "PUT ADCR, DBF" instruction is executed.
ADCSOFT 0 1
A/D operation mode selection flag Successive mode Single mode
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-14. A/D Converter Control Register (2/2)
RF: 20 H Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 Bit 1 0 Bit 0 ADCSTRT Read = R, write = W
ADCSTRT 0
Start of A/D operation Initial status or during A/D conversion. Cleared to 0 automatically after A/D
1
conversion (successive or single modeNote) starts.
Note
With the PD17134A subseries, ADCR is reset to 0 if the ADCSTRT flag is set, regardless of the A/D conversion mode. In the single mode, start conversion by writing a value to ADCR.
RF: 22H Bit 3 Bit 2 Bit 1 Bit 0 ADCCH3 ADCCH2 ADCCH1 ADCCH0 Read/write Initial value when reset 0 0 R/W 0 0 Read = R, write = W
ADCCH1 ADCCH0 0 0 1 1 0 1 0 1
Analog input channel selection ADC0 is selected. ADC1 is selected. ADC2 is selected. ADC3 is selected.
Fixed to 0. (Dummy flag)
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CHAPTER 13 PERIPHERAL HARDWARE
13.3.3 Setting Values in the 8-bit Data Register (ADCR) A value is set in the 8-bit data register via the data buffer (DBF) using the PUT instruction in the same way as for comparison voltage setting in the single mode. The peripheral address for the 8-bit data register (ADCR) of the A/D converter is assigned to 04H. If a value is sent to ADCR by the PUT instruction, only the low-order 8 bits (DBF1, DBF0) of DBF are valid. DBF3 and DBF2 values do not affect ADCR. Figure 13-15. Setting a Value in the 8-Bit Data Register (ADCR) Example of setting 6CH in ADCR CONTDATL CONTDATH DAT DAT MOV MOV PUT 0CH 06H ; CONTDATL is assigned to 0CH by using a symbol definition instruction. ; CONTDATH is assigned to 06H by using a symbol definition instruction.
DBF0, #CONTDATL; DBF1, #CONTDATH; ADCR, DBF ; Data is transferred using reserved words ADCR and DBF.
Data buffer DBF3 b3 b2 b1 b0 b3 DBF2 b2 b1 b0 b3 0 DBF1 b2 1 b1 1 b0 0 b3 1 DBF0 b2 1 b1 0 b0 0
Don't care
Don't care
8-bit data PUT ADCR, DBF ADCR (Peripheral address 04H) b7 0 b6 1 b5 1 b4 0 b3 1 b2 1 b1 0 b0 0
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CHAPTER 13 PERIPHERAL HARDWARE
13.3.4 Reading Values from the 8-bit Data Register (ADCR) A value is read from the 8-bit data register (ADCR) via the data buffer (DBF) using the GET instruction. The 8-bit data register (ADCR) of the A/D converter has peripheral address 04H and only its low-order 8 bits (DBF1, DBF0) are valid. Execution of the GET instruction does not affect the high-order 8 bits of DBF. Figure 13-16. Reading Values from the 8-bit Data Register (ADCR) The result from 8-bit A/D conversion is E2H. GET DBF, ADCR ; Example of using reserved words DBF and ADCR
Data buffer DBF3 b3 b2 b1 b0 b3 DBF2 b2 b1 b0 b3 1 DBF1 b2 1 b1 1 b0 0 b3 0 DBF0 b2 0 b1 1 b0 0
Retained
Retained
GET DBF, ADCR 8-bit data ADCR (Peripheral address 04H) b7 1 b6 1 b5 1 b4 0 b3 0 b2 0 b1 1 b0 0
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CHAPTER 13 PERIPHERAL HARDWARE
13.3.5 A/D Converter Operation The A/D converter operates in two modes: successive mode and single mode. The mode can be switched by setting the ADCSOFT flag.
ADCSOFT 0 1 Operation mode of A/D converter Successive mode (A/D conversion) Single mode (Compare operation)
Figure 13-17. Relationship between the Analog Input Voltage and Digital Conversion Result
Ideal conversion result FFH
FEH
Digital conversion result
FDH
N
03H
02H
01H
00H 0
(x VDD) 1 256 2 256 N 256 Analog input voltage (V) 254 256 255 256 256 256
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CHAPTER 13 PERIPHERAL HARDWARE
(1) Successive mode (a) Outline of successive mode In the successive mode, the A/D converter performs conversion in 8-bit units by means of successive approximation, and the result of the conversion is automatically stored to an 8-bit data register (ADCR). An analog input voltage and the voltage output by the internal D/A converter are compared by the internal comparator, and data for conversion is sequentially obtained from 8 bits of data, starting from the most significant bit. A time of 25 instructions is required to complete converting the 8 bits of data. The completion of the 8-bit A/D conversion is indicated by setting of the ADCEND flag to 1. (b) Operation in successive mode When ADCSOFT = 0, the A/D converter is set in the successive mode. By setting P0CnIDI to 1 before starting A/D conversion, use of a pin used as an analog input pin of the A/D converter as a port pin is prohibited. This is to prevent an increase in the through current of the input buffer of the port if the voltage of the pin specified as an analog input pin reaches the intermediate level. After that, an analog input signal is selected by ADCCH1 and ADCCH0. A/D conversion is started by setting the ADCSTRT flag to 1. The ADCSTRT flag is cleared to 0 immediately after A/D conversion has been started. While A/D conversion is in progress, the internal hardware performs successive approximation, starting from the most significant bit of the 8 bits of data. The conversion result is stored to an 8-bit data register on a bit-by-bit basis. Converting 1 bit of data requires a time of three instructions. If a resolution of 8 bits is not required, therefore, the time required can be calculated from the number of instructions executed, and the data being converted can be extracted before the ADCEND flag is set. The completion of the A/D conversion is indicated by setting of the ADCEND flag which takes place as soon as data has been stored to the least significant bit of the 8-bit data register.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-18. Using the Successive Mode for the A/D Converter
Set the successive mode (ADCSOFT = 0)
Set the port input disable flag of the pin used for analog input (Set P0CnIDI to 1. n = 0 to 3)
Select the analog input channel (Set ADCCH1 or ADCCH0)
Start A/D conversion (Set ADCSTRT to 1)
Wait for the completion of A/D conversion (Wait for ADCEND to be set)
Read the A/D conversion results (Execute GET for the 8-bit data register)
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CHAPTER 13 PERIPHERAL HARDWARE
(c) Successive mode A/D conversion timing Figure 13-16 shows the A/D conversion timing in the successive mode. Figure 13-19. A/D Conversion Timing in the Continuous Mode
Number of instruction to be executed (Instruction cycle) POKE 1 2 3 4 5 6 7 8 9 24 GET
Sampling Set ADCSTRT
Sampling
Sampling Read ADCR
ADCSTRT
ADCEND
8-bit data register
Previous data
Initial value 80H
Most significant bit determined
High-order 2 bits are determined
All eight bits are vaild.
Caution Sampling is executed eight times while A/D conversion is performed once. Therefore, if the analog input voltage changes substantially during A/D conversion, conversion is not performed accurately. To obtain the accurate conversion result, it is necessary to keep changes in the analog input voltage as small as possible during A/D conversion. One sampling time = 14/fx (1.75 s, 8 MHzNote) Sampling repeat cycle = 48/fx (6 s, 8 MHzNote) Note The guaranteed oscillation range of the PD17134A, 17136A, and 17P136A is 400 kHz to 2.4 MHz.
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CHAPTER 13 PERIPHERAL HARDWARE
Table 13-1. Data Conversion Time for the A/D Converter
Number of instructions executed after ADCSTRT is set to 1Note 4 instructions 7 instructions 10 instructions 13 instructions 16 instructions 19 instructions 22 instructions 25 instructions
Bits for which A/D conversion is completed (valid bits when ADCR is read) Most significant bit High-order 2 bits High-order 3 bits High-order 4 bits High-order 5 bits High-order 6 bits High-order 7 bits All 8 bits
Note Includes GET instruction to read data from ADCR. (2) Single Mode (a) Overview of single mode In the single mode, data in the 8-bit data register (ADCR) is compared with voltage subjected to D/A conversion and with an analog input signal from a pin. The comparison result appears in the ADCCMP flag. (b) Explanation of single mode operation If ADCSOFT is 1, the A/D converter function enters the single mode. Before single mode operation starts, port input is disabled for the pin to be used for analog input by setting P0CnIDI to 1. (This is done for the same reason as in the successive mode.) To start single mode operation, execute a write instruction (PUT ADCR, DBF) for the 8-bit data register (ADCR) when ADCSOFT is 1. The comparison result in single mode appears in ADCCMP at the execution of the third instruction after a PUT instruction is executed to write to the 8-bit data register (ADCR). At this time, the ADCEND flag becomes undefined.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-20. Using the Single Mode for the A/D Converter
Set single mode (ADCSOFT = 1)
Disable port input for pin to be used for analog input (Set P0CnIDI to 1)
Select analog input channel (Set ADCCH0 or ADCCH1)
Comparison data in ADCR?
NO
YES
Read the contents of ADCR into DBF (GET DBF, ADCR)
Set comparison data in DBF
Execute write instruction for 8-bit data register (PUT ADCR, DBF)
Read ADCCMP flag when third instruction is executed and read comparison result
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CHAPTER 13 PERIPHERAL HARDWARE
(c) Single mode operation (comparison) timing Figure 13-21. Single Mode Operation (Comparison) Timing
Number of instruction executed (instruction cycle)
PUT
1
2
PEEK
PUT
1
2
PEEK
Sampling Set comparison data in ADCR. ADCEND Undefined Read ADCCMP.
Sampling Set comparison data in ADCR. Read ADCCMP.
ADCCMP
Previous data
Comparison result
Comparison result
In the single mode, comparison is started when compare data is set to ADCR (by executing the PUT instruction), and the result of conversion can be read by using the PEEK instruction after execution of the third instruction. The ADCCMP flag is cleared to 0 when an instruction that writes ADCR is executed. Caution Before setting a value to ADCR, be sure to set ADCSOFT to 1. A value cannot be set to ADCR while ADCSOFT is 0 (the "PUT ADCR, DBF" instruction is invalidated). One sampling time = 14/fX (1.75 s, fX = 8 MHz)
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CHAPTER 13 PERIPHERAL HARDWARE
13.4 SERIAL INTERFACE (SIO) The serial interface consists of an shift register (SIOSFR, 8 bits), serial mode register, and serial clock counter. It is used for serial data input/output. 13.4.1 Functions of the Serial Interface This serial interface provides three signal lines: serial clock input pin (SCK), serial data output pin (SO), and serial data input pin (SI). It allows 8 bits to be sent or received in synchronization with clocks. It can be connected to peripheral input/output devices using any method with a mode compatible to that used by the PD7500 series or 75X series. (1) Serial clock Three types of internal clocks and one type of external clock are able to be selected. If an internal clock is selected as a shift clock, it is automatically output to the P0D0/SCK pin. Table 13-2. Serial Clock List
SIOCK1 0 0 1 1 SIOCK0 0 1 0 1 Serial clock to be selected External clock from SCK pin fX/16 fX/128 fX/1024
fX: System Clock oscillation frequency
(2) Transfer operation Each pin of port 0D (P0D0/SCK, P0D1/SO, and P0D2/SI) functions as a serial interface pin when SIOEN is set to 1. If SIOTS is set to 1 at this time, the operation is started in synchronization with the falling of the external or internal clock. If SIOTS is set, IRQSIO is automatically cleared. Transfer is started from the most significant bit of the shift register in synchronization with the falling of the serial clock, and the information on the SI pin is stored to the shift register, starting from the least significant bit, in synchronization with the rising of the serial clock. When transfer of 8-bit data has been completed, SIOTS is automatically cleared, and IRQSIO is set. Remark When executing serial transfer, transfer is started only from the most significant bit of the shift register. It cannot be started from the least significant bit. The status of the SI pin is loaded to the shift register in synchronization with the rising of the serial clock.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-22. Block Diagram of the Serial Interface
P0D2/SI
LSB Shift register (SIOSFR)
MSB Clear SIOTS SIOHIZ SIOCK1 SIOCK0 IRQSIO clear signal
P0D1/SO Output latch
Note
Single shot P0D0/SCK Serial clock counter Carry Clear S Q R P0D0 output latch Selector IRQSIO set signal
Selector
fSYS/1024
fSYS/128
SIOEN
P0DBIO0
P0DBIO1
Note The output latch of the shift register is shared with P0D1. If an output instruction is executed to P0D1, therefore, the status of the output latch of the shift register is accordingly changed.
142
fSYS/16
Serial start
CHAPTER 13 PERIPHERAL HARDWARE
13.4.2 3-wire Serial Interface Operation Modes Two modes can be used for the serial interface. If the serial interface function is selected, the P0D2/SI pin always takes in data in synchronization with the serial clock. * 8-bit transmission reception mode (simultaneous transmission and reception) * 8-bit reception mode (SO pin: in the high-impedance state) Table 13-3. Operating Mode of the Serial Interface
SIOEN 1 1 0 x: Don't care SIOHIZ 0 1 x P0D2/SI pin SI SI P0D2 (I/O) P0D1/SO pin SO P0D1 (input) P0D1 (I/O) Operating mode of the serial interface 8-bit transmission/reception mode 8-bit reception mode General-purpose port mode
(1) Clock synchronization 8-bit transmission and reception mode (simultaneous transmission and reception) Serial data input/output is controlled by a serial clock. The MSB of the shift register is output from the SO line at a falling edge of the serial clock (SCK pin signal). The contents of the shift register is shifted one bit at a rising edge and at the same time, data on the SI line is loaded into the LSB of the shift register. Every time the serial clock counter (3-bit counter) counts eight serial clocks, the interrupt request flag (IRQSIO1) is set to 1. Figure 13-23. Timing of 8-Bit Transmission and Reception Mode (Simultaneous Transmission and Reception)
SCK pin
1
2
3
4
5
6
7
8
SI pin
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO pin
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQSIO
Transmission starts in synchronization with the SCK pin falling edge. An instruction which writes 1 into SIOTS is executed. (Transmission start indication)
Transmission completion
Remark DI: Serial data input DO: Serial data output
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CHAPTER 13 PERIPHERAL HARDWARE
(2) Clock synchronization 8-bit transmission and reception mode (SO pin output high impedance) The P0D1/SO pin goes into a high-impedance state when SIOHIZ = 1. If supply of the serial clock is started by writing "1" to SIOTS at this time, only the reception function of the serial interface is enabled. Because the P0D1/SO pin goes into a high-impedance state, it can be used as an input port pin (P0D1). Figure 13-24. Timing of the Clock Synchronization 8-Bit Reception Mode
SCK pin
1
2
3
4
5
6
7
8
SI pin
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z SO pin
IRQSIO
Transmission starts in synchronization with an SCK pin falling edge. An instruction which writes 1 into SIOTS is executed. (Transmission start indication)
Transmission completion
Remark DI: Serial data input (3) Operation stop mode If the value in SIOTS (RF: address 02H, bit 3) is 0, the serial interface enters operation stop mode. In this mode, no serial transfer occurs. In this mode, the shift register does not perform shifting and can be used as an ordinary 8-bit register.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-25. Serial Interface Control Register (1/2)
RF: 02H Bit 3 SIOTS Read/write Initial value when reset 0 0 Bit 2 SIOHIZ Bit 1 SIOCK1 Bit 0 SIOCK0 Read = R, write = W 0 0
R/W
SIOCK1 SIOCK0 0 0 1 1 0 1 0 1
Selection of the serial clock External clock (SCK pin) fX/16 fX/128 fX/1024
SIOHIZ 0 1
Function selection of the P0D1/SO pin Serial data output (SO pin) Input port output high impedance (P0D1 pin)
SIOTS 0
Start and stop of serial transmission (at writing) Forced termination of the shift register (Disables intermediate restart). Start of serial transfer operation * At internal clock selection
1
Starts operation specifying the internal division signal of the system clock as a serial clock. * At external clock selection Starts operation in synchronization with an SCK pin falling edge.
Remark SIOTS is automatically cleared to 0 when serial transmission is completed.
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CHAPTER 13 PERIPHERAL HARDWARE
Figure 13-25. Serial Interface Control Register (2/2)
RF: 0BH Bit 3 TM0OSEL Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 Bit 1 0 Bit 0 SIOEN Read = R, write = W
SIOEN 0
SIO operation enable The pins P0D0/SCK, P0D1/SO, P0D2/SI function as ports. The pins P0D0/SCK, P0D1/SO, P0D2/SI function as the serial interface.
1
Remark See also CHAPTER 12.
TM0OSEL 0 1
Selecting function of the P0D3/TM0OUT pin The P0D3/TM0OUT pin is used as a port. The P0D3/TM0OUT pin is used for timer 0 output.
Caution This is not related to the serial interface directly.
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CHAPTER 13 PERIPHERAL HARDWARE
13.4.3 Setting Values in the Shift Register Values are set in the shift register via the data buffer (DBF) using the PUT instruction. The peripheral address of the shift register is 01H. When sending a value to the shift register using the PUT instruction, only the low-order 8 bits (DBF1, DBF0) of DBF are valid. The DBF3 and DBF2 values do not affect the shift register. Figure 13-26. Setting a Value in the Shift Register Example of setting value 64H in the shift register SIODATL DAT 4H MOV DBF0, #SIODATL MOV DBF1, #SIODATH PUT SIOSFR, DBF ; SIODATL is assigned to 4H using symbol definition. ; SIODATH is assigned to 6H using symbol definition. ; ; ; Value is transmitted using reserved word SIOSFR.
SIODATH DAT 6H
Data buffer DBF3 b3 b2 b1 b0 b3 DBF2 b2 b1 b0 b3 0 DBF1 b2 1 b1 1 b0 0 b3 0 DBF0 b2 1 b1 0 b0 0
Don't care
Don't care
8-bit data
PUT SIOSFR, DBF
SIOSFR (Peripheral address 01H) b7 0 b6 1 b5 1 b4 0 b3 0 b2 1 b1 0 b0 0
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CHAPTER 13 PERIPHERAL HARDWARE
13.4.4 Reading Values from the Shift Register A value is read from the shift register via the data buffer (DBF) using the GET instruction. The shift register has peripheral address 01H and only the low-order 8 bits (DBF1, DBF0) are valid. Executing the GET instruction does not affect the high-order 8 bits of DBF. Figure 13-27. Reading a Value from the Shift Register GET DBF, SIOSFR; Example of using reserved words DBF and SIOSFR
Data buffer DBF3 b3 b2 b1 b0 b3 DBF2 b2 b1 b0 b3 0 DBF1 b2 1 b1 1 b0 0 b3 0 DBF0 b2 1 b1 0 b0 0
Retained
Retained
GET DBF, SIOSFR 8-bit data SIOSFR (Peripheral address 01H) b7 0 b6 1 b5 1 b4 0 b3 0 b2 1 b1 0 b0 0
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CHAPTER 14
INTERRUPT FUNCTIONS
The PD17134A subseries has four internal interrupt functions and one external interrupt function. It can be used in various applications. The interrupt control circuit of the PD17134A subseries has the features listed below. This circuit enables very high-speed interrupt processing. (a) Used to determine whether an interrupt can be accepted with the interrupt mask enable flag (INTE) and interrupt enable flag (IPxxx). (b) The interrupt request flag (IRQxxx) can be tested or cleared. (Interrupt generation can be checked by software.) (c) Multiple interrupts are possible (up to three levels). (d) Standby mode (STOP, HALT) can be released by an interrupt request. (Release source can be selected by the interrupt enable flag.) Caution In interrupt processing, the bank register and the BCD, CMP, CY, Z, and IXE flags are saved in the stack automatically by the hardware for up to three levels of multiple interrupts. The DBF and WR are not saved by the hardware when peripheral hardware such as the timers or A/D converter is accessed in interrupt processing. It is recommended that the DBF and WR be saved in RAM by the software at the beginning of interrupt processing. Saved data can be loaded back into the DBF and WR immediately before the end of interrupt processing.
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CHAPTER 14 INTERRUPT FUNCTIONS
14.1 INTERRUPT SOURCE TYPES AND VECTOR ADDRESSES For every interrupt in the PD17134A subseries, when the interrupt is accepted, a branch occurs to the vector address associated with the interrupt source. This method is called the vectored interrupt method. Table 14-1 lists the interrupt source types and vector addresses. If two or more interrupts occur simultaneously, or if two or more pending interrupts are enabled at the same time, processing is performed according to the priorities shown in Table 14-1. Table 14-1. Interrupt Source Types
Vector address 0005H Internal/ external External
Interrupt source INT pin (RF: 0FH, bit 0)
Priority 1
IRQ flag IRQ RF: 3FH, bit 0 IRQTM0 RF: 3EH, bit 0
IP flag IP RF: 2FH, bit 0 IPTM0 RF: 2FH, bit 1 IPTM1 RF: 2FH, bit 2 IPBTM RF: 2FH, bit 3 IPSIO RF: 2EH, bit 0
IEG flag IEGMD0,1 RF: 1FH
Remarks Rising edge or falling edge can be selected.
Timer 0
2
0004H
Internal -
Timer 1
3
0003H
IRQTM1 RF: 3DH, bit 0 IRQBTM RF: 3CH, bit 0 IRQSIO RF: 3BH, bit 0
Internal -
Basic interval timer
4
0002H
-
Internal
Serial interface
5
0001H
-
Internal
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CHAPTER 14 INTERRUPT FUNCTIONS
14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT The flags of the interrupt control circuit are explained below. (1) Interrupt Request Flag and the Interrupt Enable Flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request occurs. When interrupt processing is executed, the flag is automatically cleared to 0. An interrupt enable flag (IPxxx) is provided for each interrupt request flag. If the flag is 1, an interrupt is enabled. If it is 0, the interrupt is disabled. (2) EI/DI instruction The EI/DI instruction is used to determine whether an accepted interrupt is to be executed. If the EI instruction is executed, the interrupt enable flag (INTE) for enabling interrupt reception is set. If the interrupt is accepted, INTE is cleared to 0. Since the INTE flag is not registered in the register file, flag status cannot be checked by instructions. The DI instruction clears the INTE flag to 0 and disables all interrupts. At reset the INTE flag is cleared to 0 and all interrupts are disabled. Table 14-2. Interrupt Request Flag and Interrupt Enable Flag
Interrupt request flag IRQ Interrupt enable flag IP
Signal for setting the interrupt request flag Set by edge detection of an INT pin input signal. A detection edge is selected by IEGMD0 or IEGMD1. Set by a match signal from timer 0. Set by a match signal from timer 1. Set by an overflow (reference time interval signal) from the basic interval timer. Set by a serial data transmission end signal from the serial interface.
IRQTM0 IRQTM1 IRQBTM
IPTM0 IPTM1 IPBTM
IRQSIO
IPSIO
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (1/6)
RF: 0FH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R 0 Note Bit 1 0 Bit 0 INT Read = R, write = W
INT 0
Status of the INT pin Sets logical status to 0 during PEEK instruction execution. Sets logical status to 1 during PEEK instruction execution.
1
Note
Values are not latched and so change momentarily according to pin logic. Once the IRQ flag is set, however, it remains set until an interrupt is accepted. The POKE instruction to address 0FH is invalid.
RF: 1FH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 Bit 1 Bit 0 IEGMD1 IEGMD0 R/W 0 0 Read = R, write = W
IEGMD1 IEGMD0 0 0 1 1 0 1 0
Selection of the interrupt detection edge of the INT pin Interrupt at the rising edge Interrupt at the falling edge Interrupt at both edges
1
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (2/6)
RF: 3FH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 When read IRQ 0 INT pin interrupt request No interrupt request has been issued from the INT pin or an INT pin interrupt is being processed. An interrupt request from the INT pin occurs or an INT pin interrupt is being held. Bit 1 0 Bit 0 IRQ Read = R, write = W
1
When write IRQ 0 INT pin interrupt request An interrupt request from the INT pin is forcibly released. An interrupt request from the INT pin is forced to occur.
1
RF: 3EH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 When read IRQTM0 0 TM0 interrupt request No interrupt request has been issued from timer 0 or a timer 0 interrupt is being processed. The contents of the timer 0 count register matches that of the timer 0 modulo register and an interrupt request occurs. Or a timer 0 interrupt request is being held. Bit 1 0 Bit 0 IRQTM0 Read = R, write = W
1
When write IRQTM0 0 TM0 interrupt request An interrupt request from timer 0 is forcibly released. An interrupt request from timer 0 is forced to occur.
1
Remark If TM0RES is set to 1, IRQTM0 is cleared to 0.
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (3/6)
RF: 3DH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 1 When read IRQTM1 0 TM1 interrupt request No interrupt request has been issued from timer 1 or a timer 1 interrupt is being processed. The contents of the timer 1 count register matches that of the timer 1 modulo register and an interrupt request occurs. Or a timer 1 interrupt request is being held. Bit 1 0 Bit 0 IRQTM1 Read = R, write = W
1
When write IRQTM1 0 TM1 interrupt request An interrupt request from timer 1 is forcibly released. An interrupt request from timer 1 is forced to occur.
1
Remark If TM1RES is set to 1, IRQTM1 is cleared to 0.
RF: 3CH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 When read IRQBTM BTM interrupt request No interrupt request has been issued from the basic interval timer or a basic interval timer interrupt is being processed. The basic interval timer overflows and an interrupt request occurs. Or a basic interval timer interrupt request is being held. Bit 1 0 Bit 0 IRQBTM Read = R, write = W
IRQTM1 is cleared to 0 also immediately after the execution of the STOP instruction.
0
1
When write IRQBTM 0 BTM interrupt request An interrupt request from the basic interval timer is forcibly released. An interrupt request from the basic interval timer is forced to occur.
1
Remark If BTMRES is set to 1, IRQBTM is cleared to 0.
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (4/6)
RF: 3BH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 When read IRQSIO 0 SIO interrupt request No interrupt request has been issued from the serial interface or a serial interface interrupt is being processed. Serial interface transmission is completed and an interrupt request occurs. Or, a serial interface Bit 1 0 Bit 0 IRQSIO Read = R, write = W
1
When write IRQSIO 0 SIO interrupt request An interrupt request from the serial interface is forcibly released. An interrupt request from the serial interface is forced to occur.
1
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (5/6)
RF: 2FH Bit 3 IPBTM Read/write Initial value when reset 0 0 Bit 2 IPTM1 Bit 1 IPTM0 Bit 0 IP Read = R, write = W 0 0
R/W
IP 0
INT pin interrupt enable Disables an interrupt from the INT pin. Holds an interrupt even if the IRQ flag is set to 1. Enables an interrupt from the INT pin. Executes the EI instruction. If the IRQ flag is set to 1, executes interrupt processing.
1
IPTM0
TM0 interrupt enable Disables an interrupt from timer 0. Holds an interrupt even if the IRQTM0 flag is set to 1. Enables an interrupt from timer 0. Executes the EI instruction. If the IRQTM0 flag is set to 1, executes interrupt processing.
0
1
IPTM1
TM1 interrupt enable Disables an interrupt from timer 1. Holds an interrupt even if the IRQTM1 flag is set to 1. Enables an interrupt from timer 1. Executes the EI instruction. If the IRQTM1 flag is set to 1, executes interrupt processing.
0
1
IPBTM
BTM interrupt enable Disables an interrupt from the basic interval timer. Holds an interrupt even if the IRQBTM flag is set to 1. Enables an interrupt from the basic interval timer. Executes the EI instruction. If the IRQBTM flag is set to 1, executes interrupt processing.
0
1
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (6/6)
RF: 2EH Bit 3 0 Read/write Initial value when reset 0 0 Bit 2 0 R/W 0 0 Bit 1 0 Bit 0 IPSIO Read = R, write = W
IPSIO
SIO interrupt enable Disables an interrupt from the serial interface.
0
Holds an interrupt even if the IRQSIO flag is set to 1. Enables an interrupt from the serial interface. Executes the EI instruction. If the IRQSIO flag is set to 1, executes interrupt processing.
1
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CHAPTER 14 INTERRUPT FUNCTIONS
14.3 INTERRUPT SEQUENCE 14.3.1 Receiving an Interrupt When an interrupt is accepted, interrupt processing starts after the instruction cycle of the instruction being executed is completed. The program flow is transferred to a vector address. However, if an interrupt occurs during MOVT or EI instruction, or if an instruction that satisfies the skip condition is executed, the interrupt processing is started two instruction cycles later. When interrupt processing starts, one level of the address stack register is consumed to store the program return address, and one level of the interrupt stack register is consumed to save BANK and PSWORD in the system register. If two or more interrupts occur or are enabled, interrupt processing is executed in descending order of priority. A lower-priority interrupt is held until a higher-priority interrupt is processed. See priorities shown in Table 14-1. Figure 14-2. Interrupt Processing Procedure
Interrupt request generation Set IRQxxx
IPxxx set? YES
NO
Hold interrupt until IPxxx is set
EI instruction executed? (INTE = 1?) YES
NO Hold interrupt until EI instruction is executed
Clear INTE flag and IRQxxx associated with accepted interrupt to 0
Decrement stack pointer by 1 (SP _ 1)
Save contents of program counter in stack pointed to by stack pointer
Load vector address into program counter
Save PSWORD content in interrupt stack
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CHAPTER 14 INTERRUPT FUNCTIONS
14.3.2 Return from the Interrupt Routine Execute the RETI instruction to return from the interrupt processing routine. During the RETI instruction cycle, processing in the figure below occurs. Figure 14-3. Return from Interrupt Processing
Execute RETI instruction
Load contents of stack pointed to by stack pointer into program counter
Load contents of interrupt-dedicated stack into PSWORD
Increment stack pointer value by one
Caution The INTE flag is not set for the RETI instruction. Interrupt processing is completed. To handle a pending interrupt successively, execute the EI instruction immediately before the RETI instruction and set the INTE flag to 1. To execute the RETI instruction following the EI instruction, no interrupt is accepted between EI instruction execution and RETI instruction execution. This is because the EI instruction sets the INTE flag to 1 after the execution of the subsequent instruction is completed. Example
EI instruction execution
Single interrupt Timer 0 interrupt processing
Timer 0 interrupt generation Timer 1 interrupt generation (held)
EI RETI
Timer 1 interrupt processing
Timer 0 interrupt generation
(held)
RETI
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CHAPTER 14 INTERRUPT FUNCTIONS
14.3.3 Interrupt Accepting Timing Figure 14-4 shows a timing chart that illustrates how interrupts are accepted. The PD17134A subseries xecutes one instruction in 16 clocks or in 1 instruction cycle. One instruction cycle consists of four states, M0 to M3, with each state made up of 4 clocks. An interrupt occurs asynchronously in respect to the program operation. The program recognizes the occurrence of the interrupt at the leading edge of state M2. Figure 14-4. Interrupt Accepting Timing (When INTE = 1, IPxxx = 1) (1/3) (1) If interrupt occurs before M2 of instruction other than MOVT and EI
Machine cycle
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
Instruction
Instruction other than MOVT and EI
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
(2) If skip condition of skip instruction is satisfied in (1)
Machine cycle
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
Instruction
Skip instruction
Treated as NOP
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
(3) If interrupt occurs after M2 of instruction other than MOVT and EI
Machine cycle
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
Instruction
Instruction other than MOVT and EI Instruction other than MOVT and EI
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-4. Interrupt Accepting Timing (When INTE = 1, IPxxx = 1) (2/3) (4) If interrupt occurs before M2 of MOVT instruction
Machine cycle
M0
M1
M2
M3
M0'
M1'
M2'
M3'
M0
M1
M2
M3
M0
M1
Instruction
MOVT instruction
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
(5) If interrupt occurs before M2' of MOVT instruction
Machine cycle
M0
M1
M2
M3
M0'
M1'
M2'
M3'
M0
M1
M2
M3
M0
M1
Instruction
MOVT instruction
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQ***
(6) If interrupt occurs before M2 of EI instruction
Machine cycle
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
Instruction
EI instruction
Instruction other than MOVT and EI
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
(7) If interrupt occurs after M2 of EI instruction
Machine cycle
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
Instruction
EI instruction
Instruction other than MOVT and EI
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-4. Interrupt Accepting Timing (When INTE = 1, IPxxx = 1) (3/3) (8) If interrupt occurs during skip of skip instruction (treated as NOP)
Machine cycle
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
M2
M3
M0
M1
Instruction
Skip instruction
Treated as NOP
INT cycle
Instruction of vector address
Occurrence of interrupt is recognized.
IRQxxx
Remarks 1. 2. 3.
The INT cycle is for preparation of an interrupt. In this cycle, the contents of PC and PSWORD are saved, and IRQxxx is cleared. The MOVT instruction exceptionally requires 2 instruction cycles. The EI instruction is designed so that multiplexed interrupt does not occur when program execution returns from interrupt processing.
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CHAPTER 14 INTERRUPT FUNCTIONS
14.4 MULTI-INTERRUPT Multi-interrupt is a method that executes interrupt processing of other interrupt source B and C during the interrupt processing for an interrupt source A as shown in Figure 14-5. Nesting level at this time is also called interrupt level. Pay attention to the following points when using multi-interrupt. (1) Priority of interrupt source (2) Limit of interrupt levels by interrupt stack (maximum 3 levels for the PD17134A subseries) Figure 14-5. Example of Multi-interrupt
Main processing EI
Interrupt processing A Interrupt processing B Interrupt disabled
EI (enables multi-interrupt)
Interrupt disabled Achievement of interrupt B Enables interrupt in interrupt processing A
Achievement of interrupt A
EI RETI Interrupt enabled Interrupt processing C
Achievement of interrupt C
Enables interrupt in interrupt processing A
Interrupt disabled
Interrupt enabled EI RETI
EI RETI
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CHAPTER 14 INTERRUPT FUNCTIONS
As shown in Figure 14-5, INTE flag is cleared automatically and becomes interrupt disable state when interrupt has been achieved. Therefore, when executing multi-interrupt processing, execute EI instruction during interrupt processing. Caution Maximum number of interrupt levels is 3. When achieving interrupt, interrupt stack register and address stack register are consumed by one level. Address stack register is consumed by MOVT instruction and PUSH instruction other than CALL instruction. Pay attention to the nesting level of address stack. 14.5 PROGRAM EXAMPLE OF INTERRUPT * Program example of countermeasure for noise reduction of external interrupt (INT pin) This example assumes the case of assigning INT pin for key input, etc. When taking into the microcomputer data in kind of switch such as key input processing, it takes some time for the level of input voltage to be stabilized after pushing the key or switch. Accordingly, the countermeasures for removing the noise generated by key, etc. should be executed by software. In the following program, after generating external interrupt, the signal from INT pin becomes effective after confirming that there is no change in the level of INT pin two times in every 100 s. Example WAITCNT CHKRAM KEYON CHK100U MEM MEM FLG FLG ORG BR ORG BR . . . . . JOB_INIT: MOV MOV INITFLG CLR1 SET1 EI . . . . . MAIN: CALL CALL . . . . . BR 55JOB 55JOB WAITCNT, #0 CHKRAM, #0 ; Clears RAM and the flag on RAM ; ; Rising edge is effective for the interrupt from INT pin IRQ IP 0.00H 0.01H 0.01H.3 0.01H.0 0H JOB_INIT 5H INT_JOB ; If key turns ON (even just once), KEYON = 1 ; CHK100U = 1 only when passing 100 s during WAIT loop ; Counter of wait processing
NOT IEGMD1, IEGMD0
MAIN
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CHAPTER 14 INTERRUPT FUNCTIONS
INT_JOB: NOP NOP ADD SKE BR SKF1 BR SKF1 BR SET1 BR WAIT_END: SET1 KEY_NO: CLR1 EI RETI CHK100U ; CHK100U 0 KEY_ON ; Judges that there is key input WAITCNT, #01 INT_JOB INT KEY_NO CHK100U WAIT_END CHK100U INT_JOB ; Loop which executes waiting for 100 s at 8 MHz ; 2 s (1 instruction) x 5 instructions x 10 times ; (count value at WAIT) ; ; ; Check the level of INT pin ; If INT pin is high level, interrupt is invalid, and returns ; to main processing ; First wait? (CHK100U = 0?) ; If it is the first time, wait again after setting CHK100U. ; In the case of the second time, finish wait processing ; WAITCNT, #0A ;
165
[MEMO]
166
CHAPTER 15 AC ZERO CROSS DETECTION
The INT pin is the interrupt signal input pin and timer count clock input pin. It also used as an AC zero cross detector input pin. This pin can be selected by writing 1 in ZCROSS (RF: 1DH bit 0). Figure 15-1. Block Diagram for the AC Zero Cross Detector
Internal bus
RF : 1DH
0 0 0 ZCROSS
INT AC
AC zero cross detector
Zero cross detection signal (To INT, TM0, BTM)
External coupling capacitor
Caution When the AC zero cross detection circuit is used, the current consumption slightly increases (to 15 A TYP.) even in the standby mode. To prevent an increase in the current consumption, clear ZCROSS to 0, and fix the input voltage of the INT pin to the high or low level. The zero cross detector consists of a high gain amplifier which uses the self-bias method. It biases the input to the switching point and causes digital displacement in response to slight displacement of INT pin input. It detects changes of an AC signal from minus to plus and vice versa. This signal is input through the external coupling capacitor. The signal changes 0 to 1 and vice versa at each displacement point.
167
CHAPTER 15 AC ZERO CROSS DETECTION
Figure 15-2. Zero Cross Detection Signal
0V AC input waveform (A)
VP-PNote
Zero cross detection signal (B)
Note
The range of the input voltage when the INT pin is used as the input pin of the AC zero cross circuit is 1.0 VP-P to 3.0 VP-P. Because the AC zero cross circuit does not have a function to reject noise, input a signal from which noise has been eliminated in advance to this circuit.
A pulse generated in the zero cross detector can be used as a timer 0 count clock and basic interval timer count clock in the same way as when the pulse does not go through the zero cross detector. The pulse is sent to the interrupt control circuit. Interrupt processing starts if an INT pin interrupt is enabled. To accept an interrupt, set IEGMD0 (RF: 1FH bit 0) and IEGMD1 (RF: 1FH bit 1) to select a signal rising edge, falling edge, or both rising and falling edges.
168
CHAPTER 16 STANDBY FUNCTION
16.1 OVERVIEW OF THE STANDBY FUNCTION The PD17134A subseries has a standby function to reduce the current consumption. The standby function can be used in two modes which can be selected as the application requires: STOP and HALT modes. In the STOP mode, the system clock is stopped. Therefore, the current consumption of the CPU in this mode is only the leakage current. This mode is effective for holding the contents of the data memory without the CPU operating. In the HALT mode, oscillation of the system clock continues, but the CPU is stopped because supply of the clock to the CPU is stopped. The current consumption in this mode is greater than in the STOP mode. However, operation can be resumed immediately after the HALT mode has been released because the system clock is oscillating. In both the STOP and HALT Modes, the contents of the data memory and registers, and the status of the output latch of the output port immediately before the standby mode is set are retained (except STOP 0000B). Therefore, set the port status to reduce the overall current consumption of the system before setting a standby mode. Table 16-1. Status in Standby Mode
STOP mode Setting instruction System clock oscillation circuit Operating status CPU RAM Port TM0 STOP instruction Oscillation stops * Operation stops * Retains previous status * Retains previous statusNote * Can operate only when INT input is selected as count pulse * Stops if system clock is selected (count value is retained) * Operation stops (count value is reset to "0") (count up is also disabled) BTM * Operation stops (count value is retained) * Can operate only when external clock is selected as serial clockNote * Operation stopsNote (ADCR 00H) * Can operate * Can operate * Can operate HALT mode HALT instruction Oscillation continues
TM1
* Can operate
SIO
* Can operate
A/D INT
* Can operate * Can operate
Note
When STOP 0000B is executed, these pins are set in the input port mode including when the multiplexed function of the pin is used.
Cautions 1. Be sure to place a NOP instruction immediately before the STOP or HALT instruction. 2. The standby mode is not set if both the interrupt request flag and interrupt enable flag are set and the interrupt is specified as the condition to release the standby mode.
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CHAPTER 16 STANDBY FUNCTION
16.2 HALT MODE 16.2.1 Setting HALT Mode The HALT mode is set when the HALT instruction is executed. Operand b3b2b1b0 of the HALT instruction specifies the condition under which the HALT mode is released. Table 16-2. HALT Mode Release Condition Format: HALT b3b2b1b0
Bit b3 b2 b1 b2 HALT mode release conditionNote 1 Enables release by IRQxxxx when 1Notes 2, 4 Fixed to "0" Enables forced release by IRQTM1 when 1Notes 3, 4 Fixed to "0"
Notes 1. 2. 3. 4.
HALT 0000B enables only reset (RESET input, power-ON/power-down reset). IPxxx must be 1. The HALT mode is released regardless of the status of IPTM1. Even if the HALT instruction is executed while IRQxxx = 1, the HALT instruction is ignored (treated as a NOP instruction), and the HALT mode is not set.
16.2.2 Start Address after HALT Mode Is Released The address from which program execution is started after the HALT mode has been released differs depending on the release condition and interrupt enable condition. Table 16-3. Start Address after HALT Mode Is Released
Release condition ResetNote 1 IRQxxxNote 2 Start address after HALT mode is released Address 0 Address next to HALT instruction in DI status Interrupt vector in EI status (if two or more IRQxxx are set, interrupt vector with highest priority)
Notes 1. 2.
RESET input and power-ON/power-down reset are valid. IPxxx must be 1 except when the HALT mode is forcibly released by IRQTM1.
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CHAPTER 16 STANDBY FUNCTION
Figure 16-1. Releasing HALT Mode (a) By RESET input
HALT instruction executed
TM1 counts up
RESET
Operation mode
HALT Mode
System reset status
WAIT
Operation mode (starts from address 0)
WAIT: Wait time until TM1 counts 256 clocks divided by 512 256 x 512/fCC + (approx. 65 ms + , fCC = 2 MHz) : Oscillation growth time (differs depending on resonator)
(b) By IRQxxx (in DI status)
HALT instruction executed
IRQxxx
Operation mode
HALT mode
Operation mode
(c) By IRQxxx (in EI status)
HALT instruction executed
Interrupt processing accepted
IRQxxx
Operation mode
HALT mode
Operation mode
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CHAPTER 16 STANDBY FUNCTION
16.2.3 HALT Mode Setting Conditions (1) Forced releasing by IRQTM1
Setting conditions Release by external clock
* Timer 0 and timer 1 are used as 16-bit timer (TM0CK1 = 1, TM0CK0 = 1, TM1CK1 = 1, * * * Timer 1 is enabled to operate * Interrupt request flag of timer 1 is cleared (IRQTM1 = 0)
TM1CK0 = 1) Timer 0 and timer 1 are enabled to operate (TM0EN = 1, TM1EN = 1) Interrupt flag of timer 1 is cleared (IRQTM1 = 0)
Release by internal clock
(2) Release by interrupt request flag (IRQxxx)
* Peripheral hardware used to release HALT mode is enabled to operate in advance.
Timer 0 Timer 1 Timer 0 + timer 1 Operation enabled (TM0EN = 1) Operation enabled (TM1EN = 1) Timer 1 selects count up signal from timer 0 as count pulse (TM1CK1 = 1, TM1CK0 = 1). Timer 0 and timer 1 are enabled to operate (TM0EN = 1, TM1EN = 1) Always enabled to operate Serial interface circuit is enabled to operate (SIOTS = 1, SIOEN = 1) Edge selected
Basic interval timer Serial interface INT pin
* *
Clear the interrupt request flag (IRQxxx) of the peripheral hardware used to release the HALT mode to 0. Set the interrupt enable flag (IPxxx) of the peripheral hardware used to release the HALT mode to 1.
Caution Be sure to include a NOP instruction immediately before the HALT instruction. By doing so, a time of one instruction is created between the IRQxxx manipulation instruction and HALT instruction. Consequently, clearing IRQxxx is correctly reflected on the HALT instruction in the case, for example, of the CLR1 IRQxxx instruction (refer to Example 1 below). Unless a NOP instruction is described immediately before the HALT instruction, the CLR1 IRQxxx instruction is not correctly reflected on the HALT instruction, and the HALT mode is not set (Example 2).
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CHAPTER 16 STANDBY FUNCTION
Example 1.
Correct program . . . . . (Setting of IRQxxx) . . . . . CLR1 NOP HALT . . . . . . . . . . 1000B IRQxxx ; Describe NOP instruction immediately before HALT instruction. ; (Clearing of IRQxxx is correctly reflected on HALT instruction.) ; Correctly execute HALT instruction (HALT mode is set).
2.
Incorrect program . . . . . (Setting of IRQxxx) . . . . . CLR1 HALT IRQxxx 1000B ; Clearing of IRQxxx is not reflected on HALT instruction. ; (It is reflected on instruction next to HALT instruction.) . . . . . . . . . . ; HALT instruction is ignored (HALT mode is not set).
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CHAPTER 16 STANDBY FUNCTION
16.3 STOP MODE 16.3.1 Setting of STOP Mode The STOP mode is set by executing the STOP instruction. The operand b3b2b1b0 of the STOP instruction specifies the condition under which the STOP mode is to be released. Table 16-4. STOP Mode Release Condition Format: STOP b3b2b1b0
Bit b3 b2 b1 b0 STOP mode release conditionNote 1 Enables release of STOP mode by IRQxxx when 1Note 2 Fixed to "0" Fixed to "0" Fixed to "0"
Notes 1. 2.
STOP 0000B enables only reset (RESET input or power-ON/power-down reset). The internal circuitry of the microcontroller is initialized to the status immediately after reset when STOP 0000B is executed. IPxxx must be 1. The STOP mode cannot be released by IRQTM1. Even if the STOP instruction is executed when IRQxxx = 1, the STOP instruction is ignored (treated as NOP), and the STOP mode is not set.
16.3.2 Start Address After STOP Mode Is Released The address from which program execution is started after the STOP mode has been released differs depending on the release condition and interrupt enable condition. Table 16-5. Start Address after STOP Mode Is Released
Release condition ResetNote 1 IRQxxxNote 2 Address 0 Address next to that of STOP instruction in DI status Interrupt vector in EI status (If two or more IRQxxx are set, interrupt vector with highest priority) Start address after STOP mode is released
Notes 1. 2.
Only RESET input and power-ON/power-down reset are valid. IPxxx must be 1. The STOP mode cannot be released by IRQTM1.
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CHAPTER 16 STANDBY FUNCTION
Figure 16-2. Releasing STOP Mode (a) Releasing STOP mode by RESET input
STOP instruction executed
TM1 counts up
RESET
Operation mode
STOP mode
System reset status
WAIT
Operation mode (starts from address 0)
WAIT: Wait time until TM1 counts 256 clocks divided by 512 256 x 512/fCC + (approx. 65 ms + , fCC = 2 MHz) : Oscillation growth time (differs depending on resonator)
(b) Releasing STOP mode by IRQxxx (in DI status)
STOP instruction executed
TM1 counts up
IRQxxx
Operation mode
STOP mode
WAIT
Operation mode
WAIT: Wait time until TM1 counts (n + 1) clocks divided by m (n + 1) x m/fCC + (n and m are values immediately before STOP mode is set) : oscillation growth time (differs depending on resonator)
(c) Releasing STOP mode by IRQxxx (in EI status)
STOP instruction executed
TM1 counts up, interrupt processing accepted
IRQxxx
Operation mode
STOP mode
WAIT
Operation mode
WAIT: Wait time until TM1 counts (n + 1) clocks divided by m (n + 1) x m/fCC + (n and m are values immediately before STOP mode is set) : oscillation growth time (differs depending on resonator)
175
CHAPTER 16 STANDBY FUNCTION
16.3.3 STOP Mode Setting Conditions When STOP mode is to be released by IRQxxx
Releasing by IRQ
Releasing by IRQSIO
Releasing by IRQTM0
* Selects edge of signal to be input from INT pin (IEGMD1, IEGMD0). * Sets modulo register value of timer 1 (that creates oscillation stabilization wait time). * Clears interrupt request flag (IRQ) of INT pin to 0. * Sets interrupt enable flag (IP) of INT pin to 1. * Selects external clock input from SCK pin as source clock (SIOCK1 = 0, SIOCK0 = 0). * Enables serial interface to operate (SIOTS = 1). * Sets modulo register value of timer 1 (that sets oscillation stabilization time). * Clears interrupt request flag of serial interface (IRQSIO) to 0. * Sets interrupt enable flag of serial interface (IPSIO) to 1. * Selects external clock input from INT pin as source clock of timer 0 (TM0CK1 = 1, TM0CK0 = 1). * Sets modulo register value of timer 0. * Sets modulo register value and source clock of timer 1 (that creates oscillation stabilization time). * Enables timer 0 to operate (TM0EN = 1). * Clears interrupt request flag (IRQTM0) to 0 * Sets interrupt enable flag of timer 0 (IPTM0) to 1.
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CHAPTER 16 STANDBY FUNCTION
Caution Be sure to include a NOP instruction before the STOP instruction. By doing so, a time of one instruction is created between the IRQxxx manipulation instruction and STOP instruction. As a result, clearing IRQxxx, for example, is correctly reflected on the STOP instruction when the IRQxxx instruction is executed (refer to Example 1 below). Unless a NOP instruction is described immediately before the STOP instruction, the CLR1 IRQxxx instruction is not reflected on the STOP instruction, and the STOP mode is not set (Example 2). Example 1. Correct program . . . . . (Setting of IRQxxx) . . . . . CLR1 NOP IRQxxx ; Describe NOP instruction immediately before the STOP instruction. ; (Clearing IRQxxx is correctly reflected on the STOP instruction.) STOP . 1000B . . . . . . . . . Incorrect program . . . . . (Setting of IRQxxx) . . . . . CLR1 STOP IRQxxx 1000B ; Clearing IRQxxx is not reflected on the STOP instruction. ; (It is reflected on the instruction next to the STOP instruction.) . . . . . . . . . . ; The STOP instruction is ignored (STOP mode is not set). ; STOP instruction is correctly executed (STOP mode is set).
2.
177
[MEMO]
178
CHAPTER 17 RESET
The PD17134A subseries is reset in the following four ways. (1) By RESET input (2) Power-ON/power-down reset that resets the microcontroller on power application or when supply voltage drops (3) Watchdog timer that resets the microcontroller in case of a program hang-up (4) Reset because of overflow/underflow of address stack The power-ON/power-down reset function is effective when the supply voltage is 4.5 to 5.5 V.
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CHAPTER 17 RESET
17.1 RESET FUNCTION The reset function is used to initialize the device operation. How the device is initialized differs depending on the type of reset effected. Table 17-1. Hardware Status at Reset
Reset method
*
RESET input during operation Internal power-ON/ power-DOWN reset during operation 0000H
*
RESET input in standby mode Internal power-ON/ power-DOWN reset in standby mode 0000H Input 0 Retains previous status Undefined 0 Retains previous status
*
Overflow of watchdog timer Overflow and underflow of stack
*
*
*
Hardware Program counter Port I/O mode Output latch General-purpose data memory Other than DBF DBF Other than WR System register WR
0000H Input Undefined Undefined Undefined 0 Undefined SP = 5H, INT = status of INT pin at that time. Others retain previous status. Timer 0: 00H, timer 1: undefined FFH Undefined (40H if watchdog timer overflows) Undefined 00H
Input 0 Undefined Undefined 0 Undefined
Control register
SP = 5H, IRQTM1 = 1, TM1EN = 1, IRQBTM = 0, and INT = status of INT pin at that time. Others are 0. Refer to CHAPTER 9 REGISTER FILE (RF). Count register 00H FFH 00H FFH Undefined
Timer 0 and timer 1 Modulo register
Counter of basic interval timer
Undefined
Shift register of serial interface (SIOSFR) Data register of A/D converter (ADCR)
Undefined 00H
Retains previous status 00H
180
CHAPTER 17 RESET
Figure 17-1. Reset Block Configuration
1
Internal bus RF : 10H 0 0 0 PDRESEN Clear
2 3 4
Internal reset signal
VDD
Power-down reset circuit Power-on reset circuit
5 6
Mask option RESET
7 8
17.2 RESETTING Operation when system reset is caused by the RESET pin is shown in the figure below. If the RESET pin is set from low to high, system clock oscillation starts and an oscillation stabilization wait occurs with the timer 1. Program execution starts from address 0000H. If power-on reset is used, the reset signals shown in Figure 17-2 are internally generated. Operation is the same as that when reset is caused externally by the RESET pin. At watchdog timer overflow reset or stack overflow and underflow reset, oscillation stabilization wait time (WAIT) does not occur. Operation starts from address 0000H after initial statuses are internally set. Figure 17-2. Reset Operation
9 10 11 12 13 14 15
RESET
TM1EN
16
TM1RES
17
Operating mode Reset WAITNote Operating mode
18 19 20
Note This is oscillation stabilization wait time. Operating mode is set when timer 1 counts system clocks (fCC) 512 x 256 counts approx. 65 ms at fCC = 2 MHz).
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CHAPTER 17 RESET
17.3 POWER-ON/POWER-DOWN RESET FUNCTION The PD17134A subseries is provided with two reset functions to prevent malfunctions from occurring in the microcontroller. They are the power-on reset function and power-down reset function. The power-on reset function resets the microcontroller when it detects that power was turned on. The power-down reset function resets the microcontroller when it detects drops in the power voltage. These functions are implemented by the power monitoring circuit whose operating voltage has a different range than the logic circuits in the microcontroller and the oscillation circuit (which stops oscillation at reset to put the microcontroller in a temporary stop state). Conditions required to enable these functions and their operations will be described next. Caution When designing an application circuit that calls for high reliability, do not depend on the internal power-ON/power-DOWN reset function only. Make sure that an external RESET signal is input. 17.3.1 Conditions Required to Enable the Power-On Reset Function This function is effective when used together with the power-down reset function. The following conditions are required to validate the power-on reset function: (1) The power voltage must be within 4.5 to 5.5 V during normal operation, including the standby state. (2) The frequency of the system clock oscillator must be 400 kHz to 4 MHz. Note (3) The power-down reset function must be enabled during normal operation, including the standby state. (4) The power voltage must rise from 0 V to the specified voltage. (5) The time it takes for the power voltage to rise from 0 to 2.7 V must be shorter than the oscillation stabilization wait time (system clock fCC = 512 x 256 counts, about 65 ms, at fCC = 2 MHz) counted in timer 1. Note Applies to the PD17135A, 17137A, and 17P137A. When the PD17134A, 17136A, or 17P136A is used, fCC = 400 kHz to 2 MHz. Cautions 1. If the above conditions are not satisfied, the power-on reset function will not operate effectively. In this case, an external reset circuit needs to be added. 2. In the standby state, even if the power-down reset function operates normally, generalpurpose data memory (except DBF) retains data up to VDD = 2.7 V. If, however, data is changed due to an external error, the data in memory is not guaranteed.
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CHAPTER 17 RESET
17.3.2 Power-On Reset Function and Operation The power-on reset function resets the microcontroller when it detects that power was turned on in the hardware, regardless of the software state. The power-on reset circuit operates under a lower voltage than the other internal circuits. It initializes the microcontroller regardless whether the oscillation circuit is operating. When the reset is terminated, timer 1 counts the number of oscillation pulses sent from the oscillator until it reaches the specified value. Within this period, oscillation becomes stable and the power voltage applied to the microcontroller enters the range (VDD = 2.7 to 5.5 V at 400 kHz to 4 MHz) in which the microcontroller is guaranteed to operate. When this period elapses, the microcontroller enters normal operation mode. Figure 17-3 shows an example of the power-on reset operation. Functions of the power-on reset (1) This circuit always monitors the voltage applied to the VDD pin. (2) This circuit resets the internal circuit of the microcomputer, regardless of whether the oscillator circuit operates or not, when the supply voltage rises, until the voltage reaches the power-ON reset clear voltage (VDD = 1.5 V TYP.).Note (3) This circuit stops oscillation during the reset operation. (4) When reset is released, timer 1 counts oscillation pulses. The microcontroller waits until oscillation becomes stable and the power voltage becomes VDD = 2.7 V or higher. Note The internal circuit of the microcontroller is not reset until the supply voltage reaches the level at which the internal circuit can operate (i.e., internal reset signal can be accepted).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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CHAPTER 17 RESET
Figure 17-3. Example of the Power-On Reset Operation
VDD (V)
5.0 2.7 A : Voltage at which oscillation starts B : Voltage at which the power-on reset operation terminates VDD
A
RESETNote 4
B
PD17134A subseries
GND
0
Time (t)
Oscillating State of oscillation Oscillation stop Oscillation start Timer 1 finishes counting
Period in which the microcontroller is guaranteed to operate
Undefined periodNote 1
Guaranteed periodNote 2
Power-on reset signal Operation state of the microcontroller
Operation stopNote 3
Waiting until oscillation becomes stable
Operating mode
Power-on reset termination
Notes 1. 2. 3.
During the operation-undefined period, not all of the operations specified for the PD17134A subseries are guaranteed. The power-on reset operation is guaranteed in this period. The operation-guaranteed period refers to the time in which all the operations specified for the
PD17134A subseries are guaranteed.
An operation stop state refers to the state in which all of the functions of the microcontroller are stopped.
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CHAPTER 17 RESET
17.3.3 Condition Required for Use of the Power-Down Reset Function The power-down reset function can be enabled or disabled using software. The following condition is required to use this function:
1 2
* The power voltage must be within 4.5 to 5.5 V during normal operation, including the standby state. * The frequency of the system clock oscillator must be 400 kHz to 4 MHz. Caution When the microcontroller is used with a power voltage of 2.7 to 4.5 V, add an external reset circuit instead of using the internal power-down reset circuit. If the internal power-down reset circuit is used with a power voltage of 2.7 to 4.5 V, reset operation may not terminate.
3 4 5
17.3.4 Power-Down Reset Function and Operation This function is enabled by setting the power-down reset enable flag (PDRESEN) using software. When this function detects a power voltage drop, it issues the reset signal to the microcontroller. It then initializes the microcontroller. Stopping oscillation during reset prevents the power voltage in the microcontroller from fluctuating out of control. When the specified power voltage recovers and the power-down reset operation is terminated, the microcontroller waits the time required for stable oscillation using the timer. The microcontroller then enters normal operation (starts from address 0). Figure 17-4 shows an example of the power-down operation. Figure 17-5 shows an example of reset operation during the period from power-down reset to power recovery. Functions of the power-down reset (1) This circuit always monitors the voltage applied to the VDD pin. (2) When this circuit detects a power voltage drop, it issues a reset signal to the other parts of the microcontroller. It continues to send this reset signal until the power voltage recovers or all the functions in the microcontroller stop. (3) This circuit stops oscillation during the reset operation to prevent software crashes. When the power voltage recovers to the low-voltage detection level (3.5 V TYP., 4.5 V MAX.) before the powerdown reset function stops, the microcontroller waits the time required for stable oscillation using timer 1, then enters normal operation mode. (4) When the power voltage recovers from 0 V, the power-on reset function has priority. (5) After the power-down reset function stops and the power voltage recovers before it reaches 0 V, the microcontroller waits using timer 1 until oscillation becomes stable and the power voltage (VDD) reaches 2.7 V. The microcontroller then enters normal operation mode.
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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CHAPTER 17 RESET
Figure 17-4. Example of the Power-Down Reset Operation
VDD (V)
5.0 4.5 Maximum voltage detected by the power-down reset function: 4.5 V Typical voltage detected by the power-down reset function: 3.5 V 3.5 2.7 C 0 Time (t) Voltage at which the power-down reset function terminates = power-on reset voltage (B): C VDD
RESET
PD17134A subseries
GND
Oscillating State of oscillation Oscillation stop
Period in which the microcontroller is guaranteed to operate Power-down reset signal
Guaranteed period
Undefined periodNote
Power-on reset signal Operation state of the microcontroller
Operating mode
Reset state Power-down reset
Note
In the operation-undefined period, not all the operations specified for the PD17134A subseries are guaranteed. The power-down reset operation, which continues to issue a reset signal until all the functions in the microcontroller stop, is guaranteed in this period.
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CHAPTER 17 RESET
Figure 17-5. Example of Reset Operation during the Period from Power-Down Reset to Power Recovery
VDD (V)
1 2 3
5.0
4 5
Maximum voltage detected by the power-down reset function: 4.5 V Typical voltage detected by the power-down reset function: 3.5 V Voltage at which the power-down reset function terminates = power-on reset voltage (B): C Time (t)
4.5
3.5 2.7 C 0
6 7 8
VDD
9 10 11
Oscillating Oscillation stop State of oscillation
Oscillating
RESET
PD17134A subseries
Guaranteed period Timer 1 finishes counting Guaranteed period
Period in which the microcontroller is guaranteed to operate Power-down reset signal
Undefined periodNote
GND
12 13 14
Power-on reset signal Operation state of the microcontroller
15 16
Operating mode Reset state Power-down reset Operating mode Waiting until oscillation becomes stable
17 18
Note
In the operation-undefined period, not all the operations specified for the PD17134A subseries are guaranteed. The power-down reset operation, which continues to issue the reset signal until all the functions in the microcontroller stop, is guaranteed in this period.
19 20
187
[MEMO]
188
CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING
The on-chip program memories of the PD17P136A and 17P137A are is a 2048 x 16-bit one-time PROM. Pins listed in Table 18-1 are used for one-time PROM writing/verifying. The address is updated by the clock signal input from the CLK pin. Caution PIB0/VPP pin is used as VPP pin in program writing/verifying mode. Therefore, there is a possibility of overrunning of the microcontroller when higher voltage than VDD + 0.3 V is applied to PIB0/VPP pin in normal operation mode. Pay careful attention to pin protection. Table 18-1. Pins Used for Writing/Verifying Program Memory
Pin VPP VDD RESET Function Applies program voltage. Apply +12.5 V to this pin. Power supply pin. Apply +6 V to this pin. System reset input pin. Used for initializing all states before setting program memory writing/verifying mode. Clock input for updating address. Updates program memory address by inputting four pulses. Select operation mode. 8-bit data I/O pins.
CLK
MD0-MD3 D0-D7
18.1 DIFFERENCES BETWEEN MASK ROM VERSION AND ONE-TIME PROM MODEL The PD17P136A and 17P137A are microcontrollers replacing the program memory of the on-chip mask ROM version PD17136A and 17137A to one-time PROM. Table 18-2 shows the differences between mask ROM version and one-time PROM version. Differences between each product are only its program memory, program size, address register size, and whether it can specify mask option or not. The CPU function and internal peripheral hardware of each product are the same. Therefore, the PD17P136A can be used for evaluating program of the PD17134A/17136A in system development. Also, the PD17P137A can be used for evaluating the PD17135A/17137A in the same way.
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CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING
Table 18-2. Differences Between Mask ROM Version and One-Time PROM Version
Item ROM 1024 x 16 bits (0000H to 03FFH) Program counter Address register Address stack register P0D, P1A, and P1B pins and pull-up resistor of RESET pin VPP pin and operating mode select pin Quality grade Not available Mask option Not available 10 bits 11 bits
PD17134A/17135A
PD17136A/17137A
PD17P136A/17P137A
One-time PROM
Mask ROM
2048 x 16 bits (0000H to 07FFH)
Provided
Standard Special [(A), (A1)]
Standard
Caution The PROM model is highly compatible with the mask ROM model in terms of functions but its internal ROM circuit and electrical characteristics are partially different from those of the mask ROM model. To replace the PROM model with the mask ROM model, thoroughly evaluate the application by using a sample of the mask ROM model. 18.2 OPERATION MODE WHEN PROGRAM MEMORY IS WRITTEN/VERIFIED The PD17P136A and 17P137A enter a program memory write/verify mode when they have been reset for a fixed time (VDD = 5 V, RESET = 0 V) and then +6 V is applied to the VDD pin and +12.5 V to the VPP pin. In this mdoe, the operation modes shown in the table below can be selected depending on the setting of the MD0 through MD3 pins. Connect VADC directly to VDD. Connect all the other pins to GND via pull-down resistor. Table 18-3. Setting Operation Modes
Setting operation mode VPP VDD MD0 H +12.5 V +6 V L L H MD1 L H L x MD2 H H H H MD3 L H H H Program memory address 0 clear Write mode Verify mode Program inhibit mode
Operation mode
Remark x: don't care (L or H)
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CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING
18.3 WRITING PROCEDURE OF PROGRAM MEMORY
1
The program memory can be written at high speeds in the following procedure.
2
(1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the unused pins to GND. Make the CLK pin low. Apply 5 V to the VDD pin. Make VPP pin and RESET pin low. Wait for 10 s. Then, apply 5 V to RESET pin. Set the program memory address 0 clear mode using mode selector pins. Apply 6 V to VDD and RESET, and 12.5 V to VPP. Set the program inhibit mode. Write data in mode for 1 ms writing. Set the program inhibit mode. Set the verify mode. If the program has been correctly written, proceed to (10). If not, repeat (7) through (9). (10) Additional writing of (number of times (x) the program has been written in (7) through (9)) x 1 ms. (11) Set the program inhibit mode. (12) Input four pulses to the CLK pin to update the program memory address by one. (13) Repeat (7) through (12) until the last address is programmed. (14) Set the program memory address 0 clear mode. (15) Change the voltage of VDD and VPP pins to 5 V. (16) Turn off the power. Figure 18-1 shows the procedures of (2) through (12). Figure 18-1. Procedure of Program Memory Writing
Repeat x times Reset Write Verify Additional writing Address increment
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VDD+1 VDD GND RESET VDD+1 VDD GND VPP VPP VDD GND VDD CLK Hi-Z D0 - D7 Hi-Z
Output data
Input data
Hi-Z Input data
Hi-Z
18 19 20
MD0
MD1
MD2
MD3
191
CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING
18.4 READING PROCEDURE OF PROGRAM MEMORY (1) (2) (3) (4) (5) (6) (7) (8) (9) Connect VADC directly to VDD, and all the other pins to GND via pull-down resistor. Make the CLK pin low. Apply 5 V to the VDD pin. Make VPP pin and RESET pin low. Wait for 10 s. Then, apply 5 V to RESET pin. Set the program memory address 0 clear mode using mode selector pins. Apply 6 V to VDD and RESET and 12.5 V to VPP. Set mode selector pins to the program inhibit mode. Set the verify mode. When clock pulses are input to the CLK pin, data for each address can be sequentially output with four clocks as one cycle. Set the program inhibit mode. Set the program memory address 0 clear mode.
(10) Change the voltage of VDD and VPP pins to 5 V. (11) Turn off the power. Figure 18-2 shows the program reading procedure (2) through (9). Figure 18-2. Procedure of Program Memory Reading
Reset
VDD+1 VDD GND RESET VDD+1 VDD GND VPP VPP VDD GND VDD CLK
D0 - D7
Hi-Z
Output data
Output data
Hi-Z
MD0
"L" MD1
MD2
MD3
192
CHAPTER 19 INSTRUCTION SET
19.1 OVERVIEW OF THE INSTRUCTION SET
b15 b14-b11 BIN 0000 0001 0010 0011 0100 0101 0110 HEX 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL RET RETSK EI DI 0111 7 RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP 1000 1001 1010 1011 1100 1101 1110 1111 8 9 A B C D E F LD SKE MOV SKNE BR r, m m, #n4 @r, m m, #n4 addr ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr m, #n4 m, #n m, #n AR AR DBF, p p, DBF WR, rf rf, WR r s h r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1
193
CHAPTER 19 INSTRUCTION SET
19.2 LEGEND AR ASR addr BANK CMP CY DBF h INTEF INTR INTSK IX MP MPE m mR mC n n4 PC p pH pL r rf rfR rfC SP s WR (!) : Address register : Address stack register indicated by stack pointer : Program memory address (11 bits) : Bank register : Compare register : Carry flag : Data buffer : Halt release condition : Interrupt enable flag : Register saved automatically to interrupt stack : Interrupt stack register : Index register : Data memory row address pointer : Memory pointer enable flag : Data memory address indicated by mR and mC : Data memory row address (high-order) : Data memory column address (low-order) : Bit position (4 bits) : Immediate data (4 bits) :Program counter : Peripheral address : Peripheral address (high-order 3 bits) : Peripheral address (low-order 4 bits) : General register column address : Register file address : Register file row address (high-order 3 bits) : Register file column address (low-order 4 bits) :Stack pointer : Stop release condition : Window register : Contents addressed by x
194
CHAPTER 19 INSTRUCTION SET
19.3 LIST OF THE INSTRUCTION SET
1
Machine code Group Mnemonic Operand Operation OP code Add ADD r, m m, #n4 ADDC r, m m, #n4 INC AR IX Subtract SUB r, m m, #n4 SUBC r, m m, #n4 Logical Operation OR r, m m, #n4 AND r, m m, #n4 XOR r, m m, #n4 Judge SKT SKF Compare SKE SKNE SKGE SKLT Rotate RORC m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 IX IX + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) V (m) (m) (m) V n4 v (r) (r) (m) v n4 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 v n = n, then skip n = 0, then skip 11110 11111 01001 01011 11001 11011 00111 mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 Operand mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
(m) (m)
(r) (r) V (m) (m) (m) V n4 CMP 0, if (m) CMP 0, if (m)
(m) -n4, skip if zero (m) -n4, skip if not zero (m) -n4, skip if not borrow (m) -n4, skip if borrow CY (r)b3 (r)b2 (r)b1 (r)b0 (r) (m) (m) (r) if MPE = 1: (MP, (r) (m) if MPE = 0: (BANK, mR, (r)) (m) if MPE = 1: (m) (MP, (r)) if MPE = 0: (m) (BANK, mR, (r)) (m) n4 SP SP -1, ASR PC, PC AR, DBF (PC), PC ASR, SP SP +1
Transfer
LD ST MOV
r, m m, r @r, m
m, @r
m, #n4 MOVT DBF, @AR
v
01000 11000 01010
mR mR mR
mC mC mC
r r r
18 19
11010
mR
mC
r
20
11101 00111 mR 000 mC 0001 n4 0000
195
CHAPTER 19 INSTRUCTION SET
Machine code Group Mnemonic Operand Operation OP code Transfer PUSH POP PEEK POKE GET PUT Branch BR AR AR WR, rf rf, WR DBF, p p, DBF addr @AR Subroutine CALL addr @AR RET RETSK RETI Interrupt EI DI Others STOP HALT NOP s h SP SP -1, ASR AR AR ASR, SP SP+1 WR (rf) (rf) WR DBF (p) (p) DBF PC addr PC AR SP SP -1, ASR PC, PC addr SP SP -1, ASR PC, PC AR PC ASR, SP SP +1 PC ASR, SP SP +1 and skip PC ASR, INTR INTSK, SP SP +1 INTEF 1 INTEF 0 STOP HALT No operation 00111 00111 00111 00111 00111 00111 01100 00111 11100 00111 00111 00111 00111 00111 00111 00111 00111 00111 000 000 001 100 000 001 010 011 100 000 000 000 rfR rfR pH pH Operand 1101 1100 0011 0010 1011 1010 addr 0100 addr 0101 1110 1110 1110 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 s h 0000 0000 0000 0000 rfC rfC pL pL
196
CHAPTER 19 INSTRUCTION SET
19.4 ASSEMBLER (AS17K) EMBEDDED MACRO INSTRUCTIONS
1
Legend
2
flag n <> : FLG type symbol : Can be omitted
Mnemonic Embedded macro SKTn SKFn SETn CLRn NOTn Operand flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n Operation if (flag 1) to (flag n) = all "1" then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n) 1 if (flag n) = "1", then (flag n) 0 if description = NOT flag n, then (flag n) 0 if description = flag n, then (flag n) 1 BANK n n 1n4 1n4 1n4 1n4 1n4
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INITFLG
flag 1, ...< flag n>
1n4
BANKn
n = 0, 1
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CHAPTER 19 INSTRUCTION SET
19.5 INSTRUCTIONS 19.5.1 Addition Instructions (1) ADD r, m <1> OP code
10 00000 mR 8 7 mC 4 3 r 0
Add data memory to general register
<2> Function When CMP = 0, (r) (r) + (m) Adds the data memory contents to the general register contents, and stores the result in general register. When CMP = 1, (r) + (m) The result is not stored in the register. Carry flag CY and zero flag Z are changed, according to the result. Sets carry flag CY, if a carry occurs as a result of the addition. Resets the carry flag, if no carry occurs. If the addition result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Addition can be executed in binary 4 bits or BCD. The BCD flag for the PSWORD specifies what kind of addition is to be executed. <3> Example 1 To add the address 0.2FH contents to the address 0.03H contents, when row address 0 (0.00H-0.0FH) in bank 0 is specified as the general register (RPH = 0, RPL = 0), and to store the result in address 0.03H: (0.03H) (0.03H) + (0.2FH) MEM003 MEM02F MEM MEM MOV MOV MOV ADD 0.03H 0.2FH BANK, #00H RPH, #00H RPL, #00H MEM003, MEM02F ; Data memory bank 0 ; General register bank 0 ; General register row address 0
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CHAPTER 19 INSTRUCTION SET
Example 2
1
To add the address 0.2FH contents to the address 0.23H contents, when row address 2 (0.20H-0.2FH) in bank 0 is specified as the general register (RPH = 0, RPL = 4), and store the result in address 0.23H: (0.23H) (0.23H) + (0.2FH) MEM023 MEM02F MEM MEM MOV MOV MOV ADD
Note RP Register RPH Bit b3 b2 b1 b0 b3 RPL b2 b1 b0 B Data 0 Bank 0 0 C Row Address D
2 3
0.23H 0.2FH BANK, #00H RPH, #00H RPL, #04H MEM023, MEM02F ; Data memory bank 0 ; General register bank 0
Note
4 5 6 7 8 9 10
; General register row address 2
RP (general register pointer) is assigned in the system register, as shown above. Therefore, to set bank 0 and row address 2 in a general register, 00H must be stored in RPH and 04H, in RPL. In this case, the subsequent arithmetic operation is executed in binary 4-bit operation, because the BCD flag is reset.
11 12 13
Example 3 To add the address 0.6FH contents to the address 0.03H contents and store the result in address 0.3H. At this time, data memory address 0.6FH can be specified, by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 4, and IXL = 0, i.e., IX = 0.40H. (0.03H) (0.03H) + (0.6FH) Address obtained as result of ORing index register contents, 0.40H, and data memory address 0.2FH MEM003 MEM02F MEM MEM MOV MOV MOV MOV MOV SET1 ADD 0.03H 0.2FH RPH, #00H RPL, #00H IXH, #00H IXM, #04H IXL, #00H IXE ; General register bank 0 ; General register row address 0 ; IX 00001000000B ; ; ; IXE flag 1 00001000000B (0.40H) 00001101111B (0.6FH) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address
14 15 16 17 18 19 20
MEM003, MEM02F ; IX
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CHAPTER 19 INSTRUCTION SET
Example 4 To add the address 0.3FH contents to the address 0.03H contents and store the result in address 0.03H. At this time, data memory address 2.3FH can be specified by specifying data memory address 2FH, if IXE = 1, IXH = 0, IXM = 1, and IXL = 0, i.e., IX = 0.10H. (0.03H) (0.03H) + (0.3FH) Address obtained as result of ORing index register contents, 0.10H, and data memory address 0.2FH MEM003 MEM02F MEM MEM MOV MOV MOV MOV MOV MOV SET1 ADD 0.03H 0.2FH BANK, #00H RPH, #00H RPL, #00H IXH, #00H IXM, #01H IXL, #00H IXE ; IXE flag 1 00000010000B (0.10H) 00100111111B (0.3FH) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address MEM003, MEM02F ; IX ; General register bank 0 ; General register row address 0 ; IX 00000010000B (0.10H) Note
Note IX Register IXH Bit b3 M Data P E 0 Bank 0 0 Row Address b2 b1 b0 b3 IXM b2 b1 b0 b3 IXL b2 b1 b0
Column address
IX (index register) is assigned in the system register, as shown above, Therefore, to specify IX = 0.10H, 00H must be stored in IXH. 01H in IXM, and 00H in IXL. In this case, MP (memory pointer) for general register indirect transfer is invalid, because the MPE flag (memory pointer enable) is reset.
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CHAPTER 19 INSTRUCTION SET
<4> Caution
1
The first operand for the ADD r, m instruction is a column address. Therefore, if the instruction is described as follows, the column address for the general register is 03H: MEM013 MEM02F MEM MEM MOV MOV ADD 0.13H 0.2FH RPH, #00H RPL, #00H MEM013, MEM02F Indicates the general register column address. The low-order 4 bits (in this case, 03H) are valid When CMP flag = 1, the addition result is not stored. When BCD flag = 1, the decimal addition result is stored. (2) ADD m, #n4 <1> OP code
10 10000 mR 8 7 mC 4 3 n4 0
2 3
; General register bank 0 ; General register row address 0
4 5 6
Add immediate data to data memory
7 8 9 10
<2> Function
11
When CMP = 0, (m) (m) + n4
12
Adds immediate data to the data memory contents, and stores the result in data memory.
13
When CMP = 1, (m) + n4 The result is not stored in the data memory. Carry flag CY and zero flag Z are changed, according to the result.
14 15
Sets carry flag CY, if a carry occurs as a result of the addition; resets the carry flag if no carry occurs. If the addition result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Addition can be executed in binary 4 bits or BCD. The BCD flag for the PSWORD specifies which kind of addition is to be executed.
16 17 18 19 20
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CHAPTER 19 INSTRUCTION SET
<3> Example 1 To add 5 to the address 0.2FH contents, and store the result in address 0.2FH: (0.2FH) (0.2FH) + 5 MEM02F MEM 0.2FH ADD Example 2 To add 5 to the address 0.6FH contents and store the result in address 0.6FH. At this time, data memory address 0.6FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 4, and IXL = 0, i.e., IX = 0.40H. (0.6FH) (0.6FH) + 05H Address obtained as result of ORing index register contents, 0.40H, and data memory address 0.2FH MEM02F MEM MOV MOV MOV MOV SET1 ADD 0.2FH BANK, #00H IXH, #00H IXM, #04H IXL, #00H IXE ; IXE flag 1 00001000000B (0.40H) 00001101111B (0.6FH) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address Example 3 To add 5 to the address 0.2FH contents and store the result in address 0.2FH. At this time, data memory address 0.2FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 0, and IXL = 0, i.e., IX = 0.00H. (0.2FH) (0.2FH) + 05H Address obtained as result of ORing index register contents, 0.00H, and data memory address 0.2FH MEM02F MEM MOV MOV MOV MOV SET1 ADD 0.2FH BANK, #00H IXH, #00H IXM, #00H IXL, #00H IXE ; IXE flag 1 00000000000B (0.00H) 00000101111B (0.2FH) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address <4> Caution When the CMP flag = 1, the addition result is not stored. When the BCD flag = 1, the decimal addition result is stored. MEM02F, #05H ; IX ; Data memory bank 0 ; IX 00000000000B MEM02F, #05H ; IX ; Data memory bank 0 ; IX 00001000000B (0.40H) MEM02F, #05H
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CHAPTER 19 INSTRUCTION SET
(3) ADDC r, m <1> OP code
10 00010 mR 8 7 mC 4 3 r 0
Add data memory to general register with carry flag
1 2 3 4 5 6 7 8 9 10 11 12
<3> Example 1 To add the 12-bit contents for addresses 0.0DH through 0.0FH to the 12-bit contents for addresses 0.2DH through 0.2FH, and store the result in the 12-bit contents for address 0.0DH to 0.0FH, when row address 0 (0.00H-0.0FH) of bank 0 is specified as a general register: (0.0FH) (0.0FH) + (0.2FH) (0.0EH) (0.0EH) + (0.2EH) + CY (0.0DH) (0.0DH) + (0.2DH) + CY MEM00D MEM00E MEM00F MEM02D MEM02E MEM02F MEM MEM MEM MEM MEM MEM MOV MOV MOV ADD ADDC ADDC 0.0DH 0.0EH 0.0FH 0.2DH 0.2EH 0.2FH BANK, RPH, RPL, #00H #00H #00H ; Data memory bank 0 ; General register bank 0 ; General register row address 0 ; Low-order nibble
<2> Function When CMP = 0, (r) (r) + (m) + CY Adds the data memory contents to the general register contents with carry flag CY, and stores the result in general register. When CMP = 1, (r) + (m) + CY The result is not stored in the register. Carry flag CY and zero flag Z are changed according to the result. By using this ADDC instruction, one or more nibbles can be easily added. Sets carry flag CY, if a carry occurs as a result of the addition; resets the carry flag if no carry occurs. If the addition result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Addition can be executed in binary 4 bits or BCD. The BCD flag for PSWORD specifies which kind of addition is to be executed.
13 14 15 16 17 18 19 20
MEM00F, MEM02F MEM00E, MEM02E
MEM00D, MEM02D ; High-order nibble
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CHAPTER 19 INSTRUCTION SET
Example 2 To shift the 12-bit contents for addresses 0.2DH through 0.2FH 1 bit to the left, when row address 2 in bank 0 (0.20H-0.2FH) is specified as a general register:
CY (carry flag)
Bank 0 Address 0DH
Bank 0 Address 0EH
Bank 0 Address 0FH
CY (carry flag)
MEM00D MEM00E MEM00F MEM02D MEM02E MEM02F
MEM MEM MEM MEM MEM MEM MOV MOV MOV ADDC ADDC ADDC
0.0DH 0.0EH 0.0FH 0.2DH 0.2EH 0.2FH RPH, #00H RPL, #04H BANK, #00H MEM00F, MEM02F MEM00E, MEM02E MEM00D, MEM02D ; General register bank 0 ; General register row address 2 ; Data memory bank 0
Example 3 To add the address 0.0FH contents to the addresses 0.40H through 0.4FH contents, and store the result in address 0.0FH: (0.0FH) (0.0FH) + (0.40H) + (0.41H) + ... + (0.4FH) MEM00F MEM000 MEM MEM MOV MOV MOV MOV MOV MOV LOOP1: SET1 ADD CLR1 INC SKE JMP IXE MEM00F, MEM000 IXE IX IXL, #0 LOOP1 ; IXE flag 0 ; IX IX + 1 ; IXE flag 1 0.0FH 0.00H BANK, #00H RPH, #00H RPL, #00H IXH, #00H IXM, #04H IXL, #00H ; Data memory bank 0 ; General register bank 0 ; General register row address 0 ; IX 00001000000B (0.40H)
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CHAPTER 19 INSTRUCTION SET
Example 4
1
To add the 12-bit contents for addresses 0.40H through 0.42H to the 12-bit contents for addresses 0.0DH through 0.0FH, and store the result in 12-bit contents for addresses 0.0DH through 0.0FH: (0.0DH) (0.0DH) + (0.40H) (0.0EH) (0.0EH) + (0.41H) + CY (0.0FH) (0.0FH) + (0.42H) + CY MEM000 MEM001 MEM002 MEM00D MEM00E MEM00F MEM MEM MEM MEM MEM MEM MOV MOV MOV MOV MOV MOV SET1 ADD ADDC ADDC (4) ADDC m, #n4 <1> OP code
10 10010 mR 8 7 mC 4 3 n4 0
2 3 4 5 6
0.00H 0.01H 0.02H 0.0DH 0.0EH 0.0FH BANK, #00H RPH, #00H RPL, #00H IXH, #00H IXM, #04H IXL, #00H IXE MEM00D, MEM000 MEM00E, MEM001 MEM00F, MEM002 ; IXE flag 1 ; (0.0DH) (0.0DH) + (0.40H) ; Low-order nibble ; (0.0EH) (0.0EH) + (0.41H) ; (0.0FH) (0.0FH) + (0.42H) ; High-order nibble Add immediate data to data memory with carry flag ; Data memory bank 0 ; General register bank 0 ; General register row address 0 ; IX 00001000000 (0.40H)
7 8 9 10 11 12 13 14 15 16 17 18 19
<2> Function When CMP = 0, (m) (m) + n4 + CY Adds immediate data to the data memory contents with carry flag (CY), and stores the result in data memory. When CMP = 1, (m) + n4 + CY The result is not stored in the data memory, and carry flag CY and zero flag Z are changed, according to the result. Sets carry flag CY, if a carry occurs as a result of the addition. Resets the carry flag, if no carry occurs. If the addition result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Addition can be executed in binary or BCD. The BCD flag for PSWORD specifies which kind of addition is to be executed.
20
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CHAPTER 19 INSTRUCTION SET
<3> Example 1 To add 5 to the 12-bit contents for addresses 0.0DH through 0.0FH, and store the result in addresses 0.0DH through 0.0FH; (0.0FH) (0.0FH) + 05H (0.0EH) (0.0EH) + CY (0.0DH) (0.0DH) + CY MEM00D MEM00E MEM00F MEM MEM MEM MOV ADD ADDC ADDC Example 2 To add 5 to the 12-bit contents for addresses 0.4DH through 0.4FH and store the result in addresses 0.4DH through 0.4FH: (0.4FH) (0.4FH) + 05H (0.4EH) (0.4EH) + CY (0.4DH) (0.4DH) + CY MEM00D MEM00E MEM00F MEM MEM MEM MOV MOV MOV MOV SET1 ADD ADDC ADDC (5) INC AR <1> OP code
10 00111 000 8 7 1001 4 3 0000 0
0.0DH 0.0EH 0.0FH BANK, #00H MEM00F, #05H MEM00E, #00H MEM00D, #00H ; Data memory bank 0
0.0DH 0.0EH 0.0FH BANK, #00H IXH, #00H IXM, #04H IXL, #00H IXE MEM00F, #5 MEM00E, #0 MEM00D, #0 ; IXE flag 1 ; (0.4FH) (0.4FH) + 5H ; (0.4EH) (0.4EH) + CY ; (0.4DH) (0.4DH) + CY Increment address register ; Data memory bank 0 ; IX 00001000000B (0.40H)
<2> Function AR AR + 1 Increments the address register AR contents.
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CHAPTER 19 INSTRUCTION SET
<3> Example 1
1
To add 1 to the 16-bit contents for AR3 through AR0 (address registers) in the system register and store the result in AR3 through AR0: AR0 AR0 + 1 AR1 AR1 + CY AR2 AR2 + CY AR3 AR3 + CY INC AR This program can be rewritten as follows, with addition instructions: ADD ADDC ADDC ADDC Example 2 To transfer table data, 16 bits (1 address) at a time, to DBF (data buffer), using the table reference instruction (for details, refer to 10.2.3 Table Reference): AR0, AR1, AR2, AR3, #01H #00H #00H #00H
2 3 4 5 6 7 8 9
; Address ORG DW DW DW DW DW . . . . . . . . MOV MOV MOV MOV LOOP: MOVT : : : : INC BR <4> Caution
Table data 10H 0F3FFH 0A123H 0FFF1H 0FFF5H 0FF11H
10 11 12 13
AR3, #0H AR2, #0H AR1, #1H AR0, #0H DBF, @AR
; Table data address ; 0010H in address register ;
14 15
; Reads table data to DBF
16 17 18 19 20
; Table data reference processing AR LOOP ; Increments address register by 1
The numbers of bits, for address registers AR3 through AR0, differ, depending on the microcontroller model to be used. * *
PD17134A/17135A
: 10 bits
PD17136A/17137A/17P136A/17P137A : 11 bits
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CHAPTER 19 INSTRUCTION SET
(6) INC IX <1> OP code
10 00111 000 8 7 1000 4 3 0000 0
Increment index register
<2> Function IX IX + 1 Increments the index register IX contents. <3> Example 1 To add 1 to the 12-bit contents for IXH, IXM, and IXL (index registers) in the system register and store the result in IXH, IXM, and IXL; IXL IXL + 1 IXM IXM + CY IXH IXH + CY INC IX This program can be rewritten as follows, with addition instructions: ADD ADDC ADDC Example 2 To clear all the contents for data memory addresses 0.00H through 0.73H, using the index register: MEM000 MOV MOV MOV RAM clear: SET1 MOV CLR1 INC SET2 SUB SUBC SUBC SKT1 BR IXE MEM000, #00H IXE IX CMP, Z IXL, #03H IXM, #07H IXH, #00H Z RAM clear ; CMP flag 1, Z flag 1 ; Checks whether index register contents ; are 73H in bank 0 ; ; Loops until contents of index register becomes ; 73H of bank 0 ; IXE flag 1 ; Writes 0 to data memory indicated by index register ; IXE flag 0 MEM0.00H IXH, #00H IXM, #00H IXL, #00H ; Sets index register contents in 00H in bank 0 ; IXL, #01H IXM, #00H IXH, #00H
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CHAPTER 19 INSTRUCTION SET
19.5.2 Subtraction Instructions
1
(1) SUB r, m <1> OP code
10 00001 mR 8 7 mC 4 3 r 0
Subtract data memory from general register
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
; ; ; Data memory bank 0 General register bank 0 General register row address 2
<2> Function When CMP = 0, (r) (r) - (m) Subtracts the data memory contents from the general register contents, and stores the result in general register. When CMP = 1, (r) - (m) The result is not stored in the register. Carry flag CY and zero flag Z are changed, according to the result. Sets carry flag CY, if a borrow occurs as a result of the subtraction. Resets the carry flag, if no borrow occurs. If the subtraction result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Subtraction can be executed in binary 4 bits or BCD. The BCD flag for PSWORD specifies which kind of subtraction is to be executed. <3> Example 1 To subtract the address 0.2FH contents from the address 0.03H contents, store the result in address 0.03H, when row address 0 (0.00H-0.0FH) in bank 0 is specified as a general register (RPH = 0, RPL = 0): (0.03H) (0.03H) + (0.2FH) MEM003 MEM02F MEM MEM SUB Example 2 To subtract the address 0.2FH contents from the address 0.23H contents, when row address 2 (0.20H- 0.2FH) in bank 0 is specified as the general register (RPH = 0, RPL = 4), and store the result in address 0.23H: (0.23H) (0.23H) - (0.2FH) MEM023 MEM02F MEM MEM MOV MOV MOV SUB 0.23H 0.2FH BANK, #00H RPH, #00H RPL, #04H MEM023, MEM02F 0.03H 0.2FH MEM003, MEM02F
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CHAPTER 19 INSTRUCTION SET
Example 3 To subtract the address 0.6FH contents from the address 0.03H contents and store result in address 0.03H. At this time, data memory address 0.6FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 4, and IXL = 0, i.e., IX = 0.40H. (0.03H) (0.03H) + (0.6FH) MEM003 MEM02F MEM MEM MOV MOV MOV MOV MOV MOV SET1 SUB 0.03H 0.2FH BANK, #00H RPH, #00H RPL, #00H IXH, #00H IXM, #04H IXL, #00H IXE MEM003, MEM02F ; Data memory bank 0 ; General register bank 0 ; General register row address 0 ; IX 00001000000B (0.40H) ; ; ; IXE flag 1 ; IX 00001000000B (0.40H) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address Example 4 To subtract the address 0.3FH contents from the address 0.03H contents and store result in address 0.03H. At this time, data memory address 0.3FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 1, and IXL = 0, i.e., IX = 0.10H. (0.03H) (0.03H) + (0.3FH) MEM003 MEM02F MEM MEM MOV MOV MOV MOV MOV MOV SET1 SUB 0.03H 0.2FH BANK #00H RPH, #00H RPL, #00H IXH, #00H IXM, #01H IXL, #00H IXE MEM003, MEM02F ; Data memory bank 0 ; General register bank 0 ; General register row address 0 ; IX 00000010000B (0.10H) ; ; ; IXE flag 1 ; IX 00000010000B (0.10H) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address 00000111111B (0.3FH) 00001101111B (0.6FH)
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CHAPTER 19 INSTRUCTION SET
<4> Caution
1
The first operand for the SUB r, m instruction is a general register address. Therefore, if the instruction is described as follows, the general register address is 03H: MEM013 MEM02F MEM MEM MOV MOV SUB 0.13H 0.2FH RPH, #00H RPL, #00H MEM013, MEM02F Specify general register in 00H-0FH range (set register pointer row address other than 1). When the CMP flag = 1, the subtraction result is not stored. When the BCD flag = 1, the decimal subtraction result is stored. (2) SUB m, #n4 <1> OP code Subtract immediate data from data memory ; General register bank 0 ; General register row address 0
2 3 4 5 6 7 8
10 10001 mR
8
7 mC
4
3 n4
0
9 10 11 12 13 14 15 16 17 18 19 20
<2> Function When CMP = 0, (m) (m) - n4 Subtracts immediate data from the data memory contents, and stores the result in data memory. When CMP = 1, (m) - n4 The result is not stored in data memory. Carry flag CY and zero flag Z are changed, according to the result. Sets carry flag CY, if a borrow occurs as a result of the subtraction. Resets the carry flag, if no borrow occurs. If the subtraction result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Subtraction can be executed in binary 4 bits or BCD. The BCD flag for PSWORD specifies which kind of subtraction is to be executed. <3> Example 1 To subtract 5 from the address 0.2FH contents, and store the result in address 0.2FH: (0.2FH) (0.2FH) - 5 MEM02F MEM SUB 0.2FH MEM02F, #05H
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CHAPTER 19 INSTRUCTION SET
Example 2 To subtract 5 from the address 0.6FH contents and store the result in address 0.6FH. At this time, data memory address 0.6FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 4, and IXL = 0, i.e., IX = 0.40H. (0.6FH) (0.6FH) - 5 Address obtained as a result of ORing index register contents, 0.40H, and data memory address 0.2FH MEM02F MEM MOV MOV MOV MOV SET1 SUB 0.2FH BANK, #00H IXH, #00H IXM, #04H IXL, #00H IXE ; Data memory bank 0 ; IX 00001000000B (0.40H) ; ; ; IXE flag 1 00001000000B (0.40H) 00001101111B (0.6FH) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address Example 3 To subtract 5 from the address 0.2FH contents and store the result in address 0.2FH. At this time, data memory address 0.2FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 0, and IXL = 0, i.e., IX = 0.00H. (0.2FH) (0.2FH) - 5 Address obtained as a result of ORing index register contents, 0.00H, and data memory address 0.2FH MEM02F MEM MOV MOV MOV MOV SET1 SUB 0.2FH BANK0, #00H IXH, #00H IXM, #00H IXL, #00H IXE ; Data memory bank 0 ; IX 00000000000B (0.00H) ; ; ; IXE flag 1 00000000000B (0.00H) 00000101111B (0.2FH) ; Bank operand OR ) 00000101111B (0.2FH) ; Specified address (3) SUBC r, m <1> OP code
10 00011 mR 8 7 mc 4 3 r 0
MEM02F, #05H ; IX
MEM02F, #05H ; IX
Subtract data memory from general register with carry flag
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CHAPTER 19 INSTRUCTION SET
<2> Function
1
When CMP = 0, (r) (r) - (m) - CY
2
Subtracts the data memory contents from the general register contents with carry flag CY. Stores the result in general register. By using this SUBC instruction, 2 or more words can be easily subtracted. When CMP = 1, (r) - (m) - CY
3 4
The result is not stored in the register. Carry flag CY and zero flag Z are changed, according to the result.
5
Sets carry flag CY, if a borrow occurs as a result of the subtraction. Resets the carry flag, if no borrow occurs. If the subtraction result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Subtraction can be executed in binary 4 bits or BCD. The BCD flag for PSWORD specifies which kind of subtraction is to be executed.
6 7 8
<3> Example 1
9
To subtract the 12-bit contents for addresses 0.2DH through 0.2FH from the 12-bit contents for addresses 0.0DH through 0.0FH and store the result in 12 bits for addresses 0.0DH through 0.0FH, when row address 0 (0.00H-0.0FH) in bank 0 is specified as a general register: (0.0FH) (0.0FH) - (0.2FH) (0.0EH) (0.0EH) - (0.2EH) - CY (0.0DH) (0.0DH) + (0.2DH) - CY MEM00D MEM00E MEM00F MEM02D MEM02E MEM02F MEM MEM MEM MEM MEM MEM SUB SUBC SUBC 0.0DH 0.0EH 0.0FH 0.2DH 0.2EH 0.2FH MEM00F, MEM02F MEM00E, MEM02E MEM00D, MEM02D ; High-order nibble ; Low-order nibble
10 11 12 13 14 15 16 17 18 19 20
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CHAPTER 19 INSTRUCTION SET
Example 2 To subtract the 12-bit contents for addresses 0.40H through 0.42H from the 12-bit contents for addresses 0.0DH through 0.0FH, and store the result in 12 bits for addresses 0.0DH through 0.0FH: (0.0DH) (0.0DH) - (0.40H) (0.0EH) (0.0EH) - (0.41H) - CY (0.0FH) (0.0FH) + (0.42H) - CY MEM000 MEM001 MEM002 MEM00D MEM00E MEM00F MEM MEM MEM MEM MEM MEM MOV MOV MOV MOV MOV MOV SET1 SUB SUBC SUBC (4) SUBC m, #n4 <1> OP code
10 10011 mR 8 7 mc 4 3 n4 0
0.00H 0.01H 0.02H 0.0DH 0.0EH 0.0FH BANK, #00H RPH, #00H RPL, #00H IXH, #00H IXM, #04H IXL, #00H IXE MEMOOD, MEM000 MEM00E, MEM001 MEM00F, MEM002 ; Data memory bank 0 ; General register bank 0 ; General register row address 0 ; IX 00001000000B (0.40H) ; ; ; IXE flag 1 ; (0.0DH) (0.0DH) - (0.40H) ; (0.0EH) (0.0EH) - (0.41H) ; (0.0FH) (0.0FH) - (0.42H)
Subtract immediate data from data memory with carry flag
<2> Function When CMP = 0, (m) (m) - n4 - CY Subtracts immediate data from the data memory contents with carry flag CY, and stores the result in data memory. When CMP = 1, (m) - n4 - CY The result is not stored in the register. Carry flag CY and zero flag Z are changed, according to the result. Sets carry flag CY, if a borrow occurs as a result of the subtraction. Resets the carry flag, if no borrow occurs. If the subtraction result is other than zero, zero flag Z is reset, regardless of compare flag CMP. If the result is zero with the compare flag reset (CMP = 0), the zero flag Z is set. If the result is zero with the compare flag set (CMP = 1), the zero flag Z is not changed. Subtraction can be executed in binary or BCD. The BCD flag for PSWORD specifies which kind of subtraction is to be executed.
214
CHAPTER 19 INSTRUCTION SET
<3> Example 1
1
To subtract 5 from the 12-bit contents for addresses 0.0DH through 0.0FH and store the result in 12 bits for addresses 0.0DH through 0.0FH: (0.0FH) (0.0FH) - 05H (0.0EH) (0.0EH) - CY (0.0DH) (0.0DH) - CY MEM00D MEM00E MEM00F MEM MEM MEM SUB SUBC SUBC Example 2 To subtract 5 from the 12-bit contents for addresses 0.4DH through 0.4FH and store the result in addresses 0.4DH through 0.4FH: (0.4FH) (0.4FH) - 05H (0.4EH) (0.4EH) - CY (0.4DH) (0.4DH) - CY MEM00D MEM00E MEM00F MEM MEM MEM MOV MOV MOV MOV SET1 SUB SUBC SUBC 0.0DH 0.0EH 0.0FH BANK, #00H IXH, #00H IXM, #04H IXL, #00H IXE MEM00F, #5 MEM00E, #0 MEM00D, #0 ; Data memory bank 0 ; IX 00001000000B (0.40H) ; ; ; IXE flag 1 ; (0.4FH) (0.4FH) - 5 ; (0.4EH) (0.4EH) - CY ; (0.4DH) (0.4DH) - CY 0.0DH 0.0EH 0.0FH MEM00F, #05H MEM00E, #00H MEM00D, #00H
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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CHAPTER 19 INSTRUCTION SET
19.5.3 Logical Operation Instructions (1) OR r, m <1> OP code
10 00110 mR 8 7 mc 4 3 r 0
OR between general register and data memory
<2> Function (r) (r) v (m) ORs the general register contents with data memory. Stores the result in general register. <3> Example 1 To OR the address 0.03H contents (1010B) and the address 0.2FH contents (0111B) and store the result (1111B) in address 0.03H: (0.03H) (0.03H) v (0.2FH)
1
0 OR
1
0
Address 03H
0
1
1
1
Address 2FH
1
1
1
1
Address 03H
MEM003 MEM MEM02F MEM MOV MOV OR (2) OR m, #n4 <1> OP code
10 10110 mR 8 7
0.03H 0.2FH MEM003, #1010B MEM02F, #0111B MEM003, MEM02F OR between data memory and immediate data
4 mc
3 n4
0
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CHAPTER 19 INSTRUCTION SET
<2> Function
1
(m) (m) v n4
2
ORs the data memory contents and immediate data. Stores the result in data memory. <3> Example 1 To set bit 3 (MSB) for address 0.03H: (0.03H) (0.03H) v 1000B
Address 0.03H 1 x x x x: don't care
3 4 5 6 7 8 9 10 11
AND between general register and data memory
MEM003
MEM OR
0.03H MEM003, #1000B
Example 2 To set all the bits for address 0.03H: MEM003 or, MEM003 MEM MOV (3) AND r, m <1> OP code
10 00100 mR 8 7 mc 4 3 r 0
MEM OR
0.03H MEM003, #1111B 0.03H MEM003, #0FH
12 13 14 15
<2> Function
v
(r) (r)
16
(m)
ANDs the general register contents with data memory and stores the result in general register.
17 18 19 20
217
CHAPTER 19 INSTRUCTION SET
<3> Example To AND the address 0.03H (1010B) contents and the address 0.2FH (0110B) contents. To store the result (0010B) in address 0.03H: (0.03H) (0.03H) (0.2FH)
1 0 1
AND 0 1 1 0 Address 2FH
0
0
1
MEM003 MEM02F
MEM MEM MOV MOV AND
(4) AND m, #n4 <1> OP code
10 11110 mR 8 7 mc 4 3 n 0
<2> Function (m) (m) n4 ANDs the data memory contents and immediate data. Stores the result in data memory. <3> Example 1 To reset bit 3 (MSB) for address 0.03H: (0.03H) (0.03H) 0111B
Address 0.03H 0 x x x x: don't care
MEM003
MEM AND
218
v
V
0
Address 03H
0
Address 03H
0.03H 0.2FH MEM003, #1010B MEM02F, #0110B MEM003, MEM02F AND between data memory and immediate data
v
0.03H MEM003, #0111B
CHAPTER 19 INSTRUCTION SET
Example 2
1
To reset all the bits for address 0.03H: MEM003 or, MEM003 MEM MOV (5) XOR r, m <1> OP code
10 00101 mR 8 7 mc 4 3 r 0
MEM AND
0.03H MEM003, #0000B 0.03H MEM003, #00H
2 3 4
Exclusive OR between general register and data memory
5 6 7 8 9 10 11
To compare the address 0.03H contents and the address 0.0FH contents. If different bits are found, set and store them in address 0.03H. If all the bits in address 0.03H are reset (i.e., the address 0.03H contents are the same as those for address 0.0FH), jumps to LBL1; otherwise, jumps to LBL2. This example is for processing to compare the status of an alternate switch (address 0.03H contents) with the internal status (address 0.0FH contents) and to branch to another processing, if the switch status changes.
<2> Function (r) (r) v (m) Exclusive-ORs the general register contents with data memory. Stores the result in general register. <3> Example 1
12 13 14
1
0
1
0
Address 03H
15 16
XOR 0 1 1 0 Address 0FH
17
1 1 0 0 Address 03H Bits changed
18 19
MEM003 MEM00F
MEM MEM XOR SKNE BR BR
0.03H 0.0FH MEM003, MEM00F MEM003, #00H LBL1 LBL2
20
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CHAPTER 19 INSTRUCTION SET
Example 2 To clear the address 0.03H contents:
0
1
0
1
Address 03H
XOR 0 1 0 1 Address 03H
0
0
0
0
Address 03H
MEM003
MEM XOR
0.03H MEM003, MEM003 Exclusive OR between data memory and immediate data
(6) XOR m, #n4 <1> OP code
10 10101 mR 8 7 mc 4 3 n4
0
<2> Function (m) (m) v n4 Exclusive-ORs the data memory contents and immediate data. Stores the result in data memory. <3> Example To invert bits 1 and 3 in address 0.03H and store the result in address 03H:
1
1
0
0
Address 03H
XOR 1 0 1 0
0
1
1
0
Address 03H Inverted bits
MEM003
MEM XOR
0.03H MEM003, #1010B
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CHAPTER 19 INSTRUCTION SET
19.5.4 Judgment Instructions
1
(1) SKT m, #n <1> OP code
10 11110 mR 8 7 mc 4 3 n 0
Skip next instruction if data memory bits are true
2 3 4 5
v
<2> Function CMP 0, if (m) n = n, then skip Skips the next one instruction, if the result of ANDing the data memory contents and immediate data is equal to n. (Executes as NOP instruction) <3> Example 1 To jump to AAA, if bit 0 in address 03H is 1; if it is 0, jumps to BBB: SKT BR BR 03H, #0001B BBB AAA
6 7 8 9 10 11 12 13
x: don't care
Example 2 To skip the next instruction, if both bits 0 and 1 in address 03H are 1. SKT 03H, #0011B
b3 Skip condition 03H x b2 x b1 1 b0 1
14 15 16 17
Example 3 The results of executing the following two instructions are the same: SKT SKE (2) SKF m, #n <1> OP code 13H, #1111B 13H, #0FH Skip next instruction if data memory bits are false
18 19
10 11111 mR 8 7 mc 4 3 n 0
20
221
CHAPTER 19 INSTRUCTION SET
<2> Function CMP 0, if (m) n = 0, then skip Skips the next one instruction, if the result of ANDing the data memory contents and immediate data is 0 (Executes as NOP instruction). <3> Example 1 To store immediate data 00H to address 0FH in the data memory, if bit 2 in address 13H is 0; if it is 1, jumps to ABC: MEM013 MEM00F MEM MEM SKF BR MOV Example 2 To skip the next instruction, if both bits 3 and 0 in address 29H are 0. SKF 29H, #1001B
b3 Skip condition 29H 0 b2 x b1 x b0 0 x: don't care
v
0.13H 0.0FH MEM013, #0100B ABC MEM00F, #00H
Example 3 The results of executing the following two instructions are the same: SKF SKE 34H, #1111B 34H, #00H
222
CHAPTER 19 INSTRUCTION SET
19.5.5 Comparison Instructions
1
(1) SKE m, #n4 <1> OP code Skip if data memory equal to immediate data
2 3
10 01001 mR 8 7 mc 4 3 n4 0
4 5
<2> Function
6
(m) -n4, skip if zero Skips the next one instruction, if the data memory contents are equal to the immediate data value (Executes as NOP instruction).
7 8
<3> Example
9
To transfer 0FH to address 24H, if the address 24H contents are 0; if not, jumps to OPE1: MEM024 MEM SKE BR MOV OPE1 (2) SKNE m, #n4 <1> OP code
10 01011 mR 8 7 mc 4 3 n4 0
0.24H MEM024, #00H OPE1 MEM024, #0FH
10 11 12
Skip if data memory not equal to immediate data
:
13 14 15 16 17 18 19 20
<2> Function (m) -n4, skip if not zero Skips the next one instruction, if the data memory contents are not equal to the immediate data value (Executes as NOP instruction).
223
CHAPTER 19 INSTRUCTION SET
<3> Example To jump to XYZ, if the asddress 1FH contents are 1 and the address 1EH contents are 3; otherwise, jump to ABC. To compare 8-bit data, this instruction is used in the following combination:
3 1EH 0 0 1 1 1FH 0 0 1 0 1
MEM01E MEM01F
MEM MEM SKNE SKE BR BR
0.1EH 0.1FH MEM01F, #01H MEM01E, #03H ABC XYZ
The above program can be rewritten as follows, using compare and zero flags: MEM01E MEM01F MEM MEM SET2 SUB SUBC SKT1 BR BR (3) SKGE m, #n4 <1> OP code
10 11001 mR 8 7 mc 4 3 n4 0
0.1EH 0.1FH CMP, Z MEM01F, #01H MEM01E, #03H Z ABC XYZ Skip if data memory greater than or equal to immediate data ; CMP flag 1, Z flag 1
<2> Function (m) -n4, skip if not borrow Skips the next one instruction, if the data memory contents are greater than or equal to the immediate data value (Executes as NOP instruction).
224
CHAPTER 19 INSTRUCTION SET
<3> Example
1
To execute RET, if 8-bit data stored in addresses 1FH (high-order) and 2FH (low-order) is greater than immediate data `17H'; if not, execute RETSK: MEM01F MEM02F MEM MEM SKGE RETSK SKNE SKLT RET RETSK MEM01F, #1 MEM02F, #8 ;7+1 0.1FH 0.2FH MEM01F, #1
2 3 4 5 6
(4) SKLT m, #n4 <1> OP code
10 11011 mR 8 7 mc 4 3 n4 0
Skip if data memory less than immediate data
7 8 9
<2> Function (m) -n4, skip if borrow
10 11
Skips the next one instruction, if the data memory contents are less than the immediate data value (Executes as NOP instruction). <3> Example To store 01H in address 0FH, if the address 10H contents are greater than immediate data `6'; if not, store 02H in address 0FH: MEM00F MEM010 MEM MEM MOV SKLT MOV 0.0FH 0.10H MEM00F, #02H MEM010, #06H MEM00F, #01H
12 13 14 15 16 17 18 19 20
225
CHAPTER 19 INSTRUCTION SET
19.5.6 Rotation Instructions (1) RORC r <1> OP code
3 00111 000 0111 r 0
Rotate right general register with carry flag
<2> Function
CY (r)b3 (r)b2 (r)b1 (r)b0
Rotates the contents of general register indicated by r to right by 1 bit including carry flag. <3> Example 1 When row address 0 of bank 0 (0.00H - 0.0FH) is specified as general register (RPH = 0, RPL = 0), rotate the value of address 0.00H (1000B) to right by 1 bit to make it 0100B. (0.00H) (0.00H) / 2 MEM000 MEM MOV MOV CLR1 RORC Example 2 When row address 0 of bank 0 (0.00H - 0.0FH) is specified as general register (RPH = 0, RPL = 0), rotate the data buffer DBF contents 0FA52H to right by 1 bit to make DBF contents 7D29H.
CY 0 1 0CH 1 1 1 1 0DH 0 1 0 0 0EH 1 0 1 0 0FH 0 1 0 CY
0.00H RPH, #00H RPL, #00H CY MEM000 ; General register bank 0 ; General register row address 0 ; CY flag 0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
0
1
0
MEM00C MEM00D MEM00E MEM00F
MEM MEM MEM MEM MOV MOV CLR1 RORC RORC RORC RORC
0.0CH 0.0DH 0.0EH 0.0FH RPH, #00H RPL, #00H CY MEM00C MEM00D MEM00E MEM00F ; General register bank 0 ; General register row address 0 ; CY flag 0
226
CHAPTER 19 INSTRUCTION SET
19.5.7 Transfer Instructions
1
(1) LD r, m <1> OP code
10 01000 mR 8 7 mc 4 3 r 0
Load data memory to general register
2 3 4 5 6 7 8
To store the address 0.2FH contents to address 0.03H: (0.03H) (0.2FH) MEM003 MEM02F MEM MEM MOV MOV LD 0.03H 0.2FH RPH, #00H RPL, #00H MEM003, MEM02F ; General register bank 0 ; General register row address 0
<2> Function (r) (m) Stores the data memory contents to general register. <3> Example 1
9 10 11 12
Bank 0 0 0 1 Row address 2 3 4 5 6 7 1 2 3 4 5
Column address 6 7 8 9 A B C D E F General register
13 14 15 16
System register
17 18 19 20
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CHAPTER 19 INSTRUCTION SET
Example 2 To store the address 0.6FH contents to address 0.03H. At this time, data memory address 0.6FH can be specified by selecting data memory address 2FH, if IXE = 1, IXH = 0, IXM = 4, and IXL = 0, i.e., IX = 0.40H. IXH 00H IXM 04H IXL 00H IXE flag 1 (0.03H) (0.6FH) Address obtained as result of ORing index register contents, 040H, and data memory contents, 0.2FH MEM003 MEM02F MEM MEM MOV MOV MOV SET1 LD
Bank 0 0 0 1 Row address 2 3 4 5 6 7 System register 1 2 3 4 5
0.03H 0.2FH IXH, #00H IXM, #04H IXL, #00H IXE MEM003, MEM02F
Column address 6 7 8 9 A B C D E F General register
; IX 00001000000B (0.40H)
; IXE flag 1
(2) ST m, r <1> OP code
10 11000 mR 8 7 mc 4 3 r 0
Store general register to data memory
<2> Function (m) (r) Stores the general register contents to data memory.
228
CHAPTER 19 INSTRUCTION SET
<3> Example 1
1
To store the address 0.03H contents to address 0.2FH: (0.2FH) (0.03H) MOV MOV ST RPH, #00H RPL, #00H 2FH, 03H
Bank 0 0 0 1
Row address
2
; General register bank 0 ; General register row address 0 ; Transfers general register contents to data memory
Column address
3 4
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F General register
5 6 7 8
2 3 4 5 6 7 System register
9
Example 2 To store the address 0.00H contents to addresses 0.18H through 0.1FH. The data memory addresses (18H - 1FH) are specified by the index register. (0.18H) (0.00H) (0.19H) (0.00H) . . . . . . . . . . . (0.1FH) (0.00H) MOV MOV MOV MEM018 MEM000 LOOP1: SET1 ST CLR1 INC SKGE BR IXE MEM018, MEM000 IXE IX IXL, #08H LOOP1 ; IXE flag 1 ; (0.1!H) (0.00H) ; IXE flag 0 ; IX IX + 1 MEM MEM IXH, #00H IXM, #00H IXL, #00H 0.18H 0.00H ; Specifies data memory address 0.00H ; IX 00000000000B (0.00H)
10 11 12 13 14 15 16 17 18 19 20
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CHAPTER 19 INSTRUCTION SET
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F General register
1
2 3 4 5 6 7 System register
(3) MOV @r, m <1> OP code
10 01010 mR 8 7 mc 4 3 r 0
Move data memory to destination indirect
<2> Function When MPE = 1 ((MP), (r)) (m) When MPE = 0 (BANK, mR, (r)) (m) Stores the data memory contents to the data memory addressed by the general register contents. When MPE = 0, transfer is performed in the same row address in the same bank. <3> Example 1 To store the address 0.20H contents to address 0.2FH with the MPE flag cleared to 0. The transfer destination data memory address is at the same row address as the transfer source, and the column address is specified by the general register contents at address 0.00H. (0.2FH) (0.20H) MEM000 MEM020 MEM MEM CLR1 MOV MOV 0.00H 0.20H MPE MEM000, #0FH @MEM000, MEM020 ; MPE flag 0 ; Sets column address in general register ; Store
230
CHAPTER 19 INSTRUCTION SET
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F General register
1
1 2 3 4
F
2 3 4 5 6 7 System register
5 6
Example 2 To store the address 0.20H contents to address 0.3FH, with the MPE flag set to 1. The row address for the transfer destination data memory address is specified by the memory pointer MP contents. The column address is specified by the general register contents at address 0.00H. (0.3FH) (0.20H) MEM000 MEM020 MEM MEM MOV MOV MOV MOV MOV SET1 MOV
Bank 0 0 0 1 F 1 2 3 4 5
7 8 9
0.00H 0.20H RPH, #00H RPL, #00H MEM000, #0FH MPH, #00H MPL, #03H MPE @MEM000, MEM020
Column address 6 7 8 9 A B C D E F General register
; General register bank 0 ; General register row address 0 ; Sets column address in general register ; Sets row address in memory pointer ; ; MPE flag 1 ; Store
10 11 12 13 14 15 16 17
Row address
2 3 4 5 6 7 System register
18
Move data memory to destination indirect
(4) MOV m, @r <1> OP code
10 11010 mR 8 7 mc 4 3 r 0
19 20
231
CHAPTER 19 INSTRUCTION SET
<2> Function When MPE = 1 (m) (MP, (r)) When MPE = 0 (m) (BANK, mR, (r)) Stores the data memory contents addressed by the general register contents to data memory. When MPE = 0, transfer is performed in the same row address in the same bank. <3> Example 1 To store the address 0.2FH contents to address 0.20H, with the MPE flag cleared to 0. The transfer destination data memory address is at the same row address as the transfer source. The column address is specified by the general register contents at address 0.00H. (0.20H) (0.2FH) MEM000 MEM020 MEM MEM CLR1 MOV MOV 0.00H 0.20H MPE MEM000, #0FH MEM020, @MEM000 ; MPE flag 0 ; Sets column address in general register ; Store
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F General register
1
F
2 3 4 5 6 7 System register
Example 2 To store the address 0.3FH contents to address 0.20H, with the MPE flag set to 1. The row address for the transfer source data memory address is specified by the memory pointer MP contents. The column address is specified by the general register contents at address 0.00H. (0.20H) (0.3FH) MEM000 MEM020 MEM MEM MOV MOV MOV SET1 MOV 0.00H 0.20H MEM000, #0FH MPH, #00H MPL, #03H MPE MEM020, @MEM000 ; Sets column address in general register ; Sets row address in memory pointer ; ; MPE flag 1 ; Store
232
CHAPTER 19 INSTRUCTION SET
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F General register
1
1 2 3 4
F
2 3 4 5 6 7 System register
5 6
(5) MOV m, #n4 <1> OP code
10 11101 mR 8 7 mc 4 3 n4 0
Move immediate data to data memory
7 8 9
<2> Function (m) n4 Stores immediate data to data memory. <3> Example 1 To store immediate data 0AH to data memory address 0.50H: (0.5H) 0AH MEM050 MEM MOV Example 2 To store immediate data 07H to address 0.32H, when data memory address 0.00H is specified with IXH = 0, IXM = 3, IXL = 2, and IXE flag = 1: (0.32H) 07H MEM000 MEM MOV MOV MOV SET1 MOV 0.00H IXH, #00H IXM, #03H IXL, #02H IXE MEM000, #07H ; IXE flag 1 ; IX 00000110010B (0.32H) 0.50H MEM050, #0AH
10 11 12 13 14 15 16 17 18 19 20
233
CHAPTER 19 INSTRUCTION SET
(6) MOVT DBF, @AR <1> OP code
10 00111 000 8 7 0001 4 3 0000 0
Move program memory data specified by AR to DBF
<2> Function SP SP - 1, ASR PC, PC AR, DBF (PC), PC ASR, SP SP + 1 Stores the program memory contents, addressed by address register AR, to data buffer DBF. Since this instruction temporarily uses one stack level, pay attention to nesting for subroutines and interrupts. <3> Example To transfer 16 bits of table data, specified by the values for address registers AR3, AR2, AR1, and AR0 in the system register, to data buffers DBF3, DBF2, DBF1, and DBF0: ;* ; ** Table data ;* ORG DW DW 0010H 0000000000000000B 1010101111001101B . . . . . . . . . . ; (0000H) ; (0ABCDH)
;* ; ** Table reference program ;* MOV MOV MOV MOV MOVT AR3, #00H AR2, #00H AR1, #01H AR0, #01H DBF, @AR ; AR3 00H Sets 0011H in address register ; AR2 00H ; AR1 01H ; AR0 01H ; Transfers address 0011H data to DBF
In this case, the data are stored in DBF, as follows: DBF3 = 0AH DBF2 = 0BH DBF1 = 0CH DBF0 = 0DH
234
CHAPTER 19 INSTRUCTION SET
(7) PUSH AR <1> OP code
Push address register
1 2
00111 000 1101 0000
3
<2> Function
4
SP SP - 1, ASR AR Decrements stack pointer SP and stores the address register AR value to address stack register specified by stack pointer. <3> Example 1 To set 003FH in address register and store it in stack: MOV MOV MOV MOV PUSH AR3, #00H AR2, #00H AR1, #03H AR0, #0FH AR
5 6 7 8 9 10 11
Bank 0 0 0 1 1 2 3 4 5
Column address 6 7 8 9 A B C D E F S T A C K
12 13 14
0 0 3 F
Row address
2 3 4 5 6 7 0 0 3 F System register
15 16 17 18 19 20
235
CHAPTER 19 INSTRUCTION SET
Example 2 To set the return address (next address of the data table) for a subroutine in the address register. Returns execution, if a data table exists after a subroutine:
............ .................. ..................
ORG
10H
SUB1: ............
SUB1 CALL ;* ;** DATA TABLE ;* DW DW DW DW 1A1FH 002FH 010AH 0555H
POP MOV MOV MOV MOV PUSH RET
AR AR3, #00H AR2, #00H AR1, #03H AR0, #00H AR
DW ORG
0FFFH 30H
If POP instruction is executed at this time, the contents of address register is "0011H" (the next address of CALL instruction).
236
CHAPTER 19 INSTRUCTION SET
(8) POP AR <1> OP code
Pop address register
1 2
00111 000 1100 0000
3
<2> Function
4
AR ASR, SP SP + 1 Pops the contents of address stack register indicated by stack pointer to address register AR and then increments stack pointer SP. <3> Example If the PSW contents are changed, while an interrupt processing routine is being executed, the PSW contents are transferred to the address register through WR at the beginning of the interrupt processing and saved to address stack register by the PUSH instruction. Before the execution returns from the interrupt routine, the address register contents are restored through WR to PSW by the POP instruction.
5 6 7 8 9 10
EI
.................... ................... ....................................................
Generates interrupt source
Interrupt processing routine
11
PEEK POKE PUSH WR, PSW AR0, WR AR
12 13 14 15 16 17 18 19 20
POP AR PEEK WR, AR0 POKE PSW, WR RET (or RETI)
...........................................
237
CHAPTER 19 INSTRUCTION SET
(9) PEEK WR, rf <1> OP code
10 00111 rfR 8 7 0011 4 3 rfC 0
Peek register file to window register
<2> Function WR (rf) Stores the register file contents to window register WR. <3> Example 1 To store the stack pointer SP contents at address 01H in the register file to the window register: PEEK WR, SP
Bank 0 0 0 1 Row address 2 3 4 5 6 7 1 2 3 4 5
Column address 6 7 8 9 A B C D E F
WR
System register
Column address 0 Row address 0 1 2 3 Register file 1 SP 2 3 4 5 6 7 8 9 A B C D E F
238
CHAPTER 19 INSTRUCTION SET
(10) POKE rf, WR <1> OP code
10 00111 rfR 8 7 0010 4 3 rfC 0
Poke window register to register file
1 2 3
<2> Function
4
(rf) WR
5
Stores the window register WR contents to register file.
6
<3> Example To store immediate data 0FH to P0DBIO for the register file through the window register: MOV POKE WR, #0FH P0DBIO, WR ; Sets all of P0D0, P0D1, P0D2, and P0D3 in output mode
7 8 9
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F
1
10 11 12 13
2 3 4 5 6 7 WR System register
14 15
Column address 0
Row address
16
A B C D E F
1
2
3
4
5
6
7
8
9
0 1 2 3 Register file P0DBIO
17 18 19 20
239
CHAPTER 19 INSTRUCTION SET
<4> Caution It seems that the same addresses 40H through 7FH of the data memory exist at addresses 40H through 7FH of the register file as for as the program is concerned. The PEEK and POKE instructions can access addresses 40H through 7FH in each data memory bank, in addition to the register file. For example, these instructions can be used as follows: MEM05F MEM PEEK POKE 0.5FH WR, PSW MEM05F, WR ; Stores PSW (7FH) contents in system register to WR ; Stores WR contents to address 5FH in data memory
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E F
1
Register file
2 3 4 5 Data memory 6 7 WR PSW POKE 5FH, WR
PEEK System register
WR, PSW
(11) GET DBF, p <1> OP code
10 00111 pH 8 7 1011 4 3 pL 0
Get peripheral data to data buffer
<2> Function DBF (p) Stores the peripheral register contents to data buffer DBF. DBF is a 16-bit area of addresses 0H through 0FH of BANK0 of the data memory regardless of the value of the bank register. <3> Example To store the 8-bit contents for shift register SIOSFR in the serial interface to data buffers DBF0 and DBF1: GET DBF, SIOSFR
240
CHAPTER 19 INSTRUCTION SET
Bank 0 0 0 1
Row address
Column address 2 3 4 5 6 7 8 9 A B C D E 1 F 2 DBF
1
1 2
Peripheral hardware register
2 3 4 5 6 7 System register SIOSFR
3 4
12H
5 6 7 8 9
<4> Caution The data buffer is configured in 16 bits. However, the number of bits accessed differs depending on the peripheral hardware. For example, if the GET instruction is executed to a peripheral hardware register with a valid bit length of 8 bits, the contents of the peripheral hardware register are stored to the low-order 8 bits (DBF1, DBF0) of the data buffer DBF.
Data buffer
DBF3 Retained
DBF2 Retained
DBF1 b7
DBF0 b0 GET
10 11
Peripheral hardware register
Actual bits b7 b0
12 13
(12) PUT p, DBF <1> OP code
10 00111 pH 8 7 1010 4 3 pL 0
Put data buffer peripheral
14 15 16 17
(p) DBF
<2> Function
18
Stores the data buffer DBF contents to peripheral hardware register. DBF is a 16-bit area of addresses 0H through 0FH of BANK0 of the data memory regardless of the value of the bank register.
19 20
241
CHAPTER 19 INSTRUCTION SET
<3> Example To set 0AH and 05H to data buffers DBF1 and DBF0, respectively, and transfer them to a peripheral register, shift register (SIOSFR) for serial interface: MOV MOV MOV PUT BANK, DBF0, DBF1, SIOSFR, #00H #05H #0AH DBF ; Data memory bank 0
Bank 0 0 0 1 1 2 3 4 5
Column address 6 7 8 9 A B C D E A F 5 DBF
Row address
2 3 4 5 6 7 System register SIOSFR
Peripheral hardware register
0A5H
<4> Caution The data buffer is configured in 16 bits. However, the number of bits accessed differs depending on the peripheral hardware. For example, if the GET instruction is executed to a peripheral hardware register with a valid bit length of 8 bits, the contents of the peripheral hardware register are stored to the low-order 8 bits (DBF1, DBF0) of the data buffer DBF.
Data buffer
DBF3 Don't care
DBF2 Don't care
b7
DBF1 b6 b5
b4
b3
DBF0 b2 b1
b0
PUT Peripheral hardware register Actual bits b7 b0
242
CHAPTER 19 INSTRUCTION SET
19.5.8 Branch Instructions
1
(1) BR addr <1> OP code
10 01100 addr 0
Branch to the address
2 3 4
<2> Function
5
PC addr
6
Branches to an address specified by addr. <3> Example FLY LAB : : BR : : BR : : BR : : BF : : LOOP1: $-3 ; Jumps to an address 3 addresses higher than current address $+2 ; Jumps to an address 2 addresses lower than current address LOOP1 ; Jumps to LOOP1 FLY ; Jumps to address 0FH 0FH ; Defines FLY = 0FH
7 8 9 10 11 12 13 14 15
(2) BR @AR <1> OP code
Branch to the address specified by address register
16 17
00111 000 0100 0000
<2> Function PC AR Branches to the program address, specified by address register AR.
18 19 20
243
CHAPTER 19 INSTRUCTION SET
<3> Example 1 To set 003FH in address register AR (AR0 - AR3) and jump to address 003FH by using the BR @AR instruction: MOV MOV MOV MOV BR AR3, AR2, AR1, AR0, @AR #00H #00H #03H #0FH ; AR3 00H ; AR2 00H ; AR1 03H ; AR0 0FH ; Jumps to address 003FH
Example 2 To change the branch destination according to the data memory address 0.10H contents, as follows: 0.10H contents 00H 01H 02H 03H 04H 05H 06H 07H 08H - 0FH ;* ; ** Jump table ;* ORG BR BR BR BR BR BR BR BR BR 10H AAA BBB CCC DDD EEE FFF GGG HHH ZZZ : : : MEM010 MEM MOV MOV MOV MOV MOV ST SKLT MOV BR 0.10H AR3, AR2, AR1, RPH, RPL, AR0, AR0, AR0, @AR #00H #00H #01H #00H #02H MEM010 #08H #08H ; Sets 08H in AR0, if AR0 contents are greater ; than 08H ; AR3 00H Sets AR to 001!H ; AR2 00H ; AR1 01H ; General register bank 0 ; General register row address 1 ; AR0 0.10H Branch destination label AAA BBB CCC DDD EEE FFF GGG HHH ZZZ
244
CHAPTER 19 INSTRUCTION SET
<4> Caution
1
The number of bits, for address register AR3, AR2, AR1, and AR0, differs, depending on the microcontroller model to be used. * PD17134A/17135A : 10 bits * PD17136A/17137A/17P136A/17P137A : 11 bits
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
245
CHAPTER 19 INSTRUCTION SET
19.5.9 Subroutine Instructions (1) CALL addr <1> OP code
10 11100 addr 0
Call subroutine
<2> Function SP SP - 1, ASR PC, PC addr Increments and stores the program counter PC value to stack, and branches to a subroutine specified by addr. <3> Example 1
MAIN ................... CALL SUB1 SUB1: .................... RET ............
Example 2
MAIN
...............
CALL SUB1
SUB1:
SUB2:
SUB3:
..............................
CALL SUB2
........... ...........
CALL SUB3
........... ...........
............
RET
RET
RET
246
CHAPTER 19 INSTRUCTION SET
(2) CALL @AR <1> OP code
Call subroutine specified by address register
1 2
00111 000 0101 0000
3
<2> Function
4
SP SP - 1, ASR PC, PC AR
5 6
Saves the program counter PC value to the stack, and branches the execution to a subroutine that starts from the address specified by address register AR. <3> Example 1
7 8
To set 0020H in address register AR (AR0-AR3) and call the subroutine at address 0020H with the CALL @AR instruction: MOV MOV MOV MOV CALL Example 2 To call the following subroutine by the data memory address 0.10H contents: Contents of 0.10H 00H 01H 02H 03H 04H 05H 06H 07H 08H-0FH Subroutine SUB1 SUB2 SUB3 SUB4 SUB5 SUB6 SUB7 SUB8 SUB9 AR3, AR2, AR1, AR0, @AR #00H #00H #02H #00H ; AR3 00H ; AR2 00H ; AR1 02H ; AR0 00H ; Calls subroutine at address 0020H
9 10 11 12 13 14 15 16 17 18 19 20
247
CHAPTER 19 INSTRUCTION SET
...........
10H SUB1 SUB2 SUB3 SUB4 SUB5 SUB6 SUB7 SUB8 SUB9 SUB1: SUB2: SUB3:
;*
;**Jump table for subroutine ;* ORG BR BR BR BR BR BR BR BR BR
....................................
....................................
....................................
...........
RET
RET
RET
SUB4:
SUB5:
SUB6:
SUB7:
SUB8:
SUB9:
RET
<4> Caution The number of bits, in address registers AR3, AR2, AR1, and AR0, differs, depending on the microcontroller model to be used. * PD17134A/17135A : 10 bits * PD17136A/17137A/17P136A/17P137A : 11 bits
.................................... ...........
MOV MOV MOV MOV MOV ST SKLT MOV CALL
RET
AR3, AR2, AR1, RPH, RPL, AR0, AR0, AR0, @AR
....................................
#00H #00H #01H #00H #02H 10H #08H #08H ; AR3 ; AR2 ; AR1 ; AR0
RET
; General register bank 0 ; General register row address 1 0.10H
; If AR0 is larger than 08H, ; set AR0 to 08H To jump table Returns here when executing RET instruction in each subroutine
....................................
00H 01H
RET
00H address register 001 * H
....................................
RET
....................................
RET
....................................
................
248
CHAPTER 19 INSTRUCTION SET
(3) RET <1> OP code
10 00111 000 8 7 1110 4 3 0000 0
Return to the main program from subroutine
1 2 3 4
PC ASR, SP SP + 1, Instruction to return to the main program from a subroutine. Restores the return address, saved to the stack by the CALL instruction, to the program counter. <3> Example
<2> Function
5 6 7 8 9
SUB1: ..............................
CALL
.................... SUB1 ....................
10 11 12 13 14 15 16
RET
(4) RETSK <1> OP code
Return to the main program then skip next instruction
00111
001
1110
0000
17
<2> Function PC ASR, SP SP + 1 and skip Instruction to return to the main program from a subroutine. Skips the instruction next to the CALL instruction (i.e., treats that instructions as an NOP instruction). Therefore, restores the return address, saved to the stack by the CALL instruction, to program counter PC and then increments the program counter.
18 19 20
249
CHAPTER 19 INSTRUCTION SET
<3> Example To execute the RET instruction, if the LSB (least significant bit) content for address 25H in the data memory (RAM) is 0. The execution is returned to the instruction next to the CALL instruction. If the LSB is 1, execute the RETSK instruction. The execution is returned to the instruction following the one next to the CALL instruction (in this example, ADD 03H, 16H).
CALL BR ADD
....................
....................
..............................
SUB1: SUB1 LOOP 03H, 16H
SKF RETSK RET
25H, #0001B ; LSB of 25H is "1" ; LSB of 25H is "0"
(5) RETI <1> OP code
Return to the main program from the interrupt service routine
00111
100
1110
0000
<2> Function PC ASR, INTR INTSK, SP SP + 1 Instruction to return to the main program, from an interrupt service routine. Restores the return address, saved to the stack by a vector interrupt, to the program counter. Part of the system register (BANK, PSWORD) is also returned to the status before the occurrence of the vector interrupt.
250
CHAPTER 19 INSTRUCTION SET
19.5.10 Interrupt Instructions
1
(1) EI <1> OP code Enable Interrupt
2 3
00111 000 1111 0000
4
<2> Function
5
INTEF 1
6
Enables a vectored interrupt. The interrupt is enabled after the instruction next to the EI instruction has been executed. <3> Example 1
7 8
As shown in the following example, the interrupt is accepted after the instruction next to that, that has accepted the interrupt, has been completely executed (excluding an instruction that manipulates program counter). The flow then shifts to the vector address
Note1.
9 10
............ EI ................
Note 2 Interrupt service routine (vector address)
11 12 13 14 15 16
....................
Generating interrupt request
MOV ADD ADD ....................... DI ...........
0AH, 0BH, 0CH,
#00H #01H #01H EI
RET
Generating interrupt request EI
17
0AH, 0BH, #01H #01H
MOV SUB ............
18 19 20
251
CHAPTER 19 INSTRUCTION SET
Notes 1. The vector address differs, depending on the interrupt to be accepted. Refer to Table 14-1. 2. The interrupt accepted in this example (an interrupt request is generated after the EI instruction has been executed and the execution flow shifts to an interrupt service routine) is the interrupt, whose interrupt enable flag (IPxxx) is set. The program flow is not changed, without the interrupt enable flag set, even if an interrupt request is generated, after the EI instruction has been executed (therefore, the interrupt is not accepted). However, interrupt request flag (IRQxxx) is set, and the interrupt is accepted, as soon as the interrupt enable flag is set. Example 2 An example of an interrupt, which occurs in response to an interrupt request being accepted counter PC is being executed:
............ EI ................
Interrupt service routine (vector address) ....................
Generating interrupt request
BR .................
ABC EI
RET
ABC:
MOV ADD .............
0AH, 0BH,
#00H #01H
(2) DI <1> OP code
Disable interrupt
00111
001
1111
0000
<2> Function INTEF 0 Instruction to disable a vectored interrupt. <3> Example Refer to Example 1 in (1) EI.
252
CHAPTER 19 INSTRUCTION SET
19.5.11 Other Instructions
1
(1) STOP s <1> OP code
3 00111 010 1111 s 0
Stop CPU and release by condition s
2 3 4
<2> Function
5
Stops the system clock and places the device in the STOP mode. In the STOP mode, the power consumption for the device is minimized. The condition, under which the STOP mode is to be released, is specified by operand (s). For the stop releasing condition (s), refer to 16.3 STOP MODE. (2) HALT h <1> OP code
3 00111 011 1111 h 0
6 7 8 9 10
Halt CPU and release by condition h
<2> Function
11
Places the device in the HALT mode. In the HALT mode, the power consumption for the device is reduced. The condition, under which the HALT mode is to be released, is specified by operand (h). For HALT releasing condition (h), refer to 16.2 HALT MODE. (3) NOP <1> OP code No operation
12 13 14 15
00111
100
1111
0000
16 17 18 19 20
<2> Function Performs nothing and consumes one machine cycle.
253
[MEMO]
254
CHAPTER 20 ASSEMBLER RESERVED WORDS
20.1 MASK OPTION DIRECTIVE The PD173134A, 17135A, 17136A, and 17137A have the following mask options. * Internal pull-up resistor of RESET pin * Internal pull-up resistor of P0D3 through P0D0 pins * Internal pull-up resistor of P1A3 through P1A0 pins * Internal pull-up resistor of P1B0 pin When developing a program, all the above mask options must be specified in the source program by using mask option directives. 20.1.1 Specifying Mask Option The mask options are described in the assembler source program by using the following directives. * OPTION and ENDOP directives * Mask option definition directive (1) OPTION and ENDOP directives These directives specify the range in which the mask option is to be described (mask option definition block). Specify the mask option by describing the mask option directive in an area between the OPTION and ENDOP directives. Description format Symbol field [label: ] Mnemonic field OPTION . . . . . . ENDOP Operand field Comment field [;comment]
255
CHAPTER 20 ASSEMBLER RESERVED WORDS
(2) Mask option definition directive Table 20-1. Mask Option Definition Directive
Option Internal pull-up resistor of RESET pin Internal pull-up resistor of P0D3 through P0D0 pins Internal pull-up resistor of P1A3 through P1A0 pins Internal pull-up resistor of P1B0 pin OPTP1B OPTP1A , ..., Note 2 OPTP0D , ..., Note 1 Definition directive and format OPTRES Operand OPEN PULLUP OPEN PULLUP OPEN PULLUP OPEN PULLUP Definition None Provided None Provided None Provided Not used Used
Notes 1. 2.
, , , and specify the mask options of the P0D3, P0D2, P0D1, and P0D0 pins, respectively. , , , and specify the mask options of the P1A3, P1A2, P1A1, and P1A0 pins, respectively.
(3) Example of describing mask option
; Example of describing mask option of PD17134A subseries MASK_OPTION: OPTION OPTRES OPTP0D OPTP1A OPTP1A ENDOP PULLUP ; Start of mask option definition block ; Internal pull-up resistor is connected to RESET pin. ; P0D1 and P0D0 are open (externally pulled up). PULLUP, OPEN, PULLUP, OPEN ; P1A3 and P1A1 pins are connected to internal pull-up resistor. ; P1A2 and P1A0 pins are open (externally pulled up). PULLUP ; P1B0 pin is connected to internal pull-up resistor. ; End of mask option definition block PULLUP, PULLUP, OPEN, OPEN ; Internal pull-up resistor is connected to P0D3 and P0D2 pins.
256
CHAPTER 20 ASSEMBLER RESERVED WORDS
20.2 RESERVED SYMBOLS
1
The reserved symbols defined in the PD17134A, 17135A, 17136A, and 17137A device file (AS17134) are listed below. System register (SYSREG)
2 3
Read/ write R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15 to 12 of the address register Bits 11 to 8 of the address register Bits 7 to 4 of the address register Bits 3 to 0 of the address register Window register Bank register Index register high Data memory row address pointer high Memory pointer enable flag Index register middle Data memory row address pointer low Index register low General register pointer high General register pointer low Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag
Symbolic name AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE
Attribute MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG
Value 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
257
CHAPTER 20 ASSEMBLER RESERVED WORDS
Data buffer (DBF)
Symbolic name DBF3 DBF2 DBF1 DBF0 Read/ write R/W R/W R/W R/W DBF bits 15 to 12 DBF bits 11 to 8 DBF bits 7 to 4 DBF bits 3 to 0
Attribute MEM MEM MEM MEM
Value 0.0CH 0.0DH 0.0EH 0.0FH
Description
Port register
Symbolic name P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P1A3 P1A2 P1A1 P1A0 P1B0 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Port 0A bit 3 Port 0A bit 2 Port 0A bit 1 Port 0A bit 0 Port 0B bit 3 Port 0B bit 2 Port 0B bit 1 Port 0B bit 0 Port 0C bit 3 Port 0C bit 2 Port 0C bit 1 Port 0C bit 0 Port 0D bit 3 Port 0D bit 2 Port 0D bit 1 Port 0D bit 0 Port 1A bit 3 Port 1A bit 2 Port 1A bit 1 Port 1A bit 0 Port 1B bit 0
Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG
Value 0.70H.3 0.70H.2 0.70H.1 0.70H.0 0.71H.3 0.71H.2 0.71H.1 0.71H.0 0.72H.3 0.72H.2 0.72H.1 0.72H.0 0.73H.3 0.73H.2 0.73H.1 0.73H.0 1.70H.3 1.70H.2 1.70H.1 1.70H.0 1.71H.0
Description
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258
CHAPTER 20 ASSEMBLER RESERVED WORDS
Register file (control register)
1
Symbolic name SP SIOTS SIOHIZ SIOCK1 SIOCK0 WDTRES WDTEN TM0OSEL SIOEN P0BGPU P0AGPU INT PDRESEN TM0EN TM0RES TM0CK1 TM0CK0 TM1EN Attribute MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.81H 0.82H.3 0.82H.2 0.82H.1 0.82H.0 0.83H.3 0.83H.0 0.8BH.3 0.8BH.0 0.8CH.1 0.8CH.0 0.8FH.0 0.90H.0 0.91H.3 0.91H.2 0.91H.1 0.91H.0 0.92H.3 0.92H.2 0.92H.1 0.92H.0 0.93H.3 0.93H.2 0.93H.1 0.93H.0 0.9BH.3 0.9BH.2 0.9BH.1 0.9BH.0 0.9CH.3 0.9CH.2 0.9CH.1 0.9CH.0 0.9DH.0 0.9FH.1 0.9FH.0 0.0A0H.0 0.0A1H.3 0.0A1H.1 0.0A1H.0 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Stack pointer SIO start flag SO pin state SIO source clock selection flag bit 1 SIO source clock selection flag bit 0 Watchdog timer reset flag Watchdog timer enable flag Flag for switching timer 0 output and port SIO enable flag P0B group pull-up selection flag (pull-up = 1) P0A group pull-up selection flag (pull-up = 1) INT pin status flag Power-down reset enable flag Timer 0 enable flag Timer 0 reset flag Timer 0 source clock selection flag bit 1 Timer 0 source clock selection flag bit 0 Timer 1 enable flag Timer 1 reset flag Timer 1 source clock selection flag bit 1 Timer 1 source clock selection flag bit 0 BTM interrupt request clock selection flag BTM reset flag BTM source clock selection flag bit 1 BTM source clock selection flag bit 0 P0C3 input port disable flag (ADC3/P0C3 selection) P0C2 input port disable flag (ADC2/P0C2 selection) P0C1 input port disable flag (ADC1/P0C1 selection) P0C0 input port disable flag (ADC0/P0C0 selection) P0C3 input/output selection flag (1 = output port) P0C2 input/output selection flag (1 = output port) P0C1 input/output selection flag (1 = output port) P0C0 input/output selection flag (1 = output port) Zerocross detector enable flag INT pin edge detection selection flag bit 1 INT pin edge detection selection flag bit 0 A/D converter start flag (always 0 when read) A/D converter software control flag (1 = single mode) A/D converter comparison result flag (valid only in single mode) A/D converter conversion end flag Description
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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TM1RES TM1CK1 TM1CK0
BTMISEL BTMRES BTMCK1 BTMCK0 P0C3IDI P0C2IDI P0C1IDI P0C0IDI P0CBIO3 P0CBIO2 P0CBIO1 P0CBIO0 ZCROSS IEGMD1 IEGMD0 ADCSTRT ADCSOFT ADCCMP ADCEND
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259
CHAPTER 20 ASSEMBLER RESERVED WORDS
Symbolic name ADCCH3 ADCCH2 ADCCH1 ADCCH0 P0DBIO3 P0DBIO2 P0DBIO1 P0DBIO0 P1AGIO P0BGIO P0AGIO IPSIO IPBTM IPTM1 IPTM0 IP IRQSIO IRQBTM IRQTM1 IRQTM0 IRQ
Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG
Value 0.0A2H.3 0.0A2H.2 0.0A2H.1 0.0A2H.0 0.0ABH.3 0.0ABH.2 0.0ABH.1 0.0ABH.0 0.0ACH.2 0.0ACH.1 0.0ACH.0 0.0AEH.0 0.0AFH.3 0.0AFH.2 0.0AFH.1 0.0AFH.0 0.0BBH.0 0.0BCH.0 0.0BDH.0 0.0BEH.0 0.0BFH.0
Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Dummy flag Dummy flag
Description
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A/D converter channel selection flag bit 1 A/D converter channel selection flag bit 0 P0D3 input/output selection flag (1 = output port) P0D2 input/output selection flag (1 = output port) P0D1 input/output selection flag (1 = output port) P0D0 input/output selection flag (1 = output port) P1A group input/output selection flag (1 = all P1As are output ports.) P0B group input/output selection flag (1 = all P0Bs are output ports.) P0A group input/output selection flag (1 = all P0As are output ports.) SIO interrupt enable flag BTM interrupt enable flag TM1 interrupt enable flag TM0 interrupt enable flag INT pin interrupt enable flag SIO interrupt request flag BTM interrupt request flag TM1 interrupt request flag TM0 interrupt request flag INT pin interrupt request flag
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Peripheral register
Symbolic name SIOSFR TM0M TM1M ADCR TM0TM1C AR
Attribute DAT DAT DAT DAT DAT DAT
Value 01H 02H 03H 04H 45H 40H
Read/ write R/W W W R/W R R/W
Description Peripheral address of the shift register Peripheral address of the timer 0 modulo register Peripheral address of the timer 1 modulo register Peripheral address of A/D converter data register Peripheral address of timer 0 timer 1 count register Peripheral address of the address register for GET, PUT, PUSH, CALL, BR, MOVT, and INC instructions
Others
Symbolic name DBF IX
Attribute DAT DAT
Value 0FH 01H
Description Fixed operand value of PUT, GET, or MOVT instruction Fixed operand value of INC instruction
260
(One-time PROM model is available for all models.)
Small general-purpose controllers
A/D : 4ch Timer : 3ch Serial interface : 1ch
Performance
Medium-voltage port AC zerocross
PD17137A PD17136A PD17135A PD17134A
ROM: 4 KB, ceramic ROM: 4KB, RC ROM: 2 KB, ceramic ROM: 2 KB, RC
APPENDIX A DEVELOPMENT OF PD171xx SUBSERIES
A/D : 4ch Timer : 3ch Serial interface : 1ch
PD17149 PD17147 PD17145
ROM: 8 KB, ceramic ROM: 4 KB, ceramic ROM: 2 KB, ceramic
Comparator : 4ch Timer : 1ch Serial interface : 1ch
PD17133 PD17132
ROM: 2 KB, ceramic ROM: 2 KB, RC
Timer : 1ch Serial interface : 1ch
PD17121 PD17120
ROM: 1.5 KB, ceramic ROM: 1.5 KB, RC
Tiny controller
ROM 1 KB ROM 1 KB
PD17103L PD17103 PD17107L PD17107
Ceramic, low-voltage: 1.8 V MIN. Ceramic RC, low-voltage: 1.5 V MIN. RC
PD17104L PD17104 PD17108L PD17108
Ceramic, low-voltage: 1.8 V MIN. Ceramic RC: low-voltage: 1.5 V MIN. RC
16
22
24
28
Number of pins
261
[MEMO]
262
APPENDIX B COMPARISON OF FUNCTIONS BETWEEN PD17135A, 17137A, AND PD17145 SUBSERIES
1 2
(1/2)
PD17145
ROM RAM Stack 2K bytes
PD17147
4K bytes 110 x 4 bits
PD17149
8K bytes
PD17135A
2K bytes
PD17137A
4K bytes
3 4 5 6 7 8
112 x 4 bits Address stack x 5 levels Interrupt stack x 3 levels
Instruction execution time (clock, supply voltage)
2 s (fX = 8 MHz, VDD = 4.5 to 5.5 V) 4 s (fX = 4 MHz, VDD = 3.6 to 5.5 V) 8 s (fX = 2 MHz, VDD = 2.7 to 5.5 V)
2 s (fX = 8 MHz, VDD = 4.5 to 5.5 V) 4 s (fX = 4 MHz, VDD = 2.7 to 5.5 V)
I/O
CMOS I/O Input Sense input 2 (P0F0, P0F1)
12 (P0A, P0B, P0C) 1 (P1B0) 1 (INT)
1 (INT) Can be pulled up by mask option 8 (P0D, P0E, voltage: VDD) P0D pull up: software P0E pull up: software
N-ch open-drain I/O
8 (P0D, P1A, voltage: 9 V) P0D pull up: mask option P1A pull up: mask option 100 k TYP. 8 bits x 4 channels (VDD = 4.5 to 5.5 V) None (VREF = VADC = VDD) 2 (timer output: TM0OUT) TM0 clock : fX/256 fX/64 fX/16 INT TM1 clock : fX/1024 fX/512 fX/256 TM0 count up 1 (multiplexed with watchdog timer) Count pulse : fX/8192 fX/4096 TM0 count up INT 1 (with AC zero cross detection function) 4 (TM0, TM1, BTM, SIO) 1 (clocked 3-wire)
9 10 11 12 13 14 15 16 17 18 19 20
Internal pull-up resistor
100 k TYP. (except P0D) 10 k TYP. (P0D) 8 bits x 4 channels (VDD = 4.0 to 5.5 V) VREF (VREF = 2.5 to VDD) 2 (timer output: TM1OUT) TM0 clock : fX/512 fX/64 fX/16 INT TM1 clock : fX/8192 fX/128 fX/16 TM0 count up 1 (multiplexed with watchdog timer) Count pulse : fX/16384 fX/4096 fX/512 fX/16 1
A/D converter (supply voltage) Reference voltage pin Timer 8 bits (TM0, TM1)
Basic interval timer (BTM)
Interrupt
External
Internal SIO Output latch
Independent of P0D1 latch
Multiplexed with P0D1 latch
263
APPENDIX B COMPARISON OF FUNCTIONS BETWEEN PD17135A, 17137A, AND PD17145 SUBSERIES
(2/2)
PD17145
Standby function
PD17147
PD17149
PD17135A
PD17137A
HALT, STOP (with input pin RLS for releasing) 128 x 256 counts Mask option 28-pin plastic SDIP (400 mil) 28-pin plastic SOP (375 mil)
HALT, STOP 512 x 256 counts Internal
Oscillation stabilization wait time POC function Package
One-time PROM
PD17P149
PD17P137A
Caution The PD17145 subseries is not pin-compatible with the PD17135A and 17137A. The PD17145 subseries has no model equivalent to the PD17134A and 17136A (RC oscillation type). For the electrical characteristics, refer to the Data Sheet of each model. Remark fX: system clock oscillation frequency
264
APPENDIX C DEVELOPMENT TOOLS
1
The following support tools are available for developing programs for the PD17134A subseries. Hardware
Name Outline These are in-circuit emulators that can be commonly used with microcontrollers in 17K series. IE-17K and IE-17K-ET are connected to a host machine, NEC PC-9800 series or IBM PC/ATTM, through RS-232-C. EMU-17K is mounted in expansion slot of NEC PC-9800 series that serves as host machine. When these in-circuit emulators are used in combination with the evaluation board (SE board) dedicated to each model of microcontroller, they operate as emulators corresponding to microcontroller. When these in-circuit emulators are used with man-machine interface software SIMPLEHOSTTM, a more sophisticated debugging environment can be created. EMU-17K also has a function that allows you to monitor data memory contents real-time. SE-17134 is an SE board for PD17134A subseries series. It can be used alone for system evaluation or in combination with an in-circuit emulator for debugging. EP-17K28CT is an emulation probe for 17K series 28-pin shrink DIP (400 mil) and connects SE board and target system. EP-17K28GT is an emulation probe for 17K series 28-pin SOP (375 mil) and connects SE board and target system by being used with EV-9500GT-28Note3. EV-9500GT-28 is an adapter for 28-pin SOP (375 mil) and is used to connect EP-17K28GT to target system. AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to PD17P136A and 17P137A. When connected with program adapter AF-9808F, these programmers can be used to program PD17P136A and 17P137A. AF-9808F is an adapter for programming PD17P136A and 17P137A, and is used in combination with AF-9703, AF-9704 or AF-9706.
2 3 4 5 6 7 8 9 10 11 12 13 14
In-circuit emulator IE-17K IE-17K-ETNote1 EMU-17KNote2
SE board (SE-17134) Emulation probe (EP-17K28CT) Emulation probe (EP-17K28GT) Conversion adapter (EV-9500GT-28Note3) PROM programmer AF-9703Note4 AF-9704Note4 AF-9705Note4 AF-9706Note4 Programmer adapter (AF-9808FNote4)
Notes 1. 2. 3. 4.
Low-price model: external power supply type This is a program of IC Corp. For details, consult IC. Two EV-9500GT-28 are supplied as accessories with the EP-17K28GT. Five EV-9500GT-28's are optionally available as a set. Manufactured by Ando Electric. For details, consult Ando Electric.
15 16 17 18 19 20
265
APPENDIX C DEVELOPMENT TOOLS
Software
Name 17K series assembler (AS17K) Description AS17K is an assembler applicable to the 17K series. In developing PD17134A, 17135A, 17136A, and 17137A programs, AS17K is used in combination with a device file (AS17134). AS17134 is a device file for the PD17134A, 17135A, 17136A, and 17137A. It is used together with the assembler (AS17K) which is applicable to the 17K series. Host machine OS Distribution media 5-inch, 2HD PC-9800 series MS-DOS
TM
Part number
S5A10AS17K S5A13AS17K S7B10AS17K S5A10AS17134 S5A13AS17134 S7B10AS17134 S5A10IE17K S5A13IE17K S7B10IE17K
3.5-inch, 2HD
IBM PC/AT
PC DOSTM
5-inch, 2HC
Device file (AS17134)
5-inch, 2HD PC-9800 series MS-DOS 3.5-inch, 2HD
IBM PC/AT
PC DOS
5-inch, 2HC
Support software (SIMPLEHOST)
SIMPLEHOST, running on the WindowsTM, provides manmachine-interface in developing programs by using a personal computer and the incircuit emulator.
5-inch, 2HD PC-9800 series MS-DOS Windows 3.5-inch, 2HD
IBM PC/AT
PC DOS
5-inch, 2HC
Remark The supported OS versions are as follows:
OS MS-DOS PC DOS Windows Version Ver. 3.30 to Ver. 5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1
Note Although MS-DOS Ver. 5.00/5.00A and PC DOS Ver. 5.0 have a task swap function, this function cannot be used with this software.
266
APPENDIX D NOTES ON CONFIGURATION OF SYSTEM CLOCK OSCILLATION CIRCUIT
1 2
The system clock oscillation circuit oscillates by using a ceramic resonator connected across the X1 and X2 pins or an oscillation resistor connected across the OSC1 and OSC0 pins. Figure D-2 shows the external circuits of the system clock oscillation circuit. Figure D-1. External Circuit of System Clock Oscillation Circuit
3 4 5
PD17135A PD17137A PD17P137A
XOUT Ceramic resonator XIN GND
PD17134A PD17136A PD17P136A
OSC0 OSC1
6 7 8
Oscillation resistor
9 10
Caution Wire the system clock oscillation circuit so that the resistance component and inductance component of the ground wiring can be minimized. Wire the portion enclosed in the dotted line in Figure D-1 as follows to prevent influence of wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Keep a distance between the wiring and a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground the wiring to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. Figure D-2 shows an examples of incorrect oscillation circuits.
11 12 13 14 15 16 17 18 19 20
267
APPENDIX D NOTES ON CONFIGURATION OF SYSTEM CLOCK OSCILLATION CIRCUIT
Figure D-2. Example of Incorrect Oscillation Circuits (a) Wiring length of circuit is too long. (b) Crossed signal lines
XOUT
XIN
GND
PORT
XOUT
XIN
GND
Too long
(c) Signal line close to high alternating current
(d) Current flowing through ground line of oscillation circuit (potential at points A and B changes in respect to point C)
XOUT
XIN
GND
PORT
XOUT
XIN
GND
High current
A
B High current
C
(e) Signal is extracted
XOUT
XIN
GND
268
APPENDIX E INSTRUCTION LIST
1
E.1 INSTRUCTION LIST (by function)
2
[Transfer Instructions] LD ST MOV MOV MOV MOVT PUSH POP PEEK POKE GET PUT r, m ... 227 m, r ... 228 @r, m ... 231 m, @r ... 231 m, #n4 ... 233 DBF, @AR ... 234 AR ... 235 AR ... 237 WR, rf ... 238 rf, WR ... 239 DBF, p ... 240 p, DBF ... 241
[Addition Instructions] ADD ADD ADDC ADDC INC INC r, m ... 198 m, #n4 ... 201 r, m ... 203 m, #n4 ... 205 AR ... 206 IX ... 208
3 4 5 6 7 8 9 10 11 12 13 14 15
[Subtraction Instructions] SUB SUB SUBC SUBC r, m ... 209 m, #n4 ... 211 r, m ... 212 m, #n4 ... 214
[Logical Operation Instructions] OR OR AND AND XOR XOR r, m ... 216 m, #n4 ... 216 r, m ... 217 m, #n4 ... 218 r, m ... 219 m, #n4 ... 220
[Branch Instructions] BR BR addr ... 243 @AR ... 243
[Subroutine Instructions] CALL CALL RET ... 249 addr ... 246 @AR ... 247
[Judgment Instructions] SKT SKF m, #n ... 221 m, #n ... 223
RETSK ... 249 RETI ... 250 [Interrupt Instructions]
[Comparison Instructions] SKE SKNE SKGE SKLT m, #n4 ... 223 m, #n4 ... 223 m, #n4 ... 224 m, #n4 ... 224
EI ... 251 DI ... 252 [Other Instructions] STOP HALT s ... 253 h ... 253
16 17 18 19 20
[Rotation Instructions] RORC r ... 226
NOP ... 253
269
APPENDIX E INSTRUCTION LIST
E.2 IINSTRUCTION LIST (alphabetical order) [A] ADD ADD ADDC ADDC AND AND [B] BR BR [C] CALL CALL [D] DI ... 252 [E] EI ... 251 [G] GET [H] HALT [I] INC INC [L] LD [M] MOV MOV MOV MOVT [N] NOP ... 253 m, #n4 ... 233 m, @r ... 231 @r, m ... 231 DBF, @AR ... 234 r, m ... 227 AR ... 206 IX ... 208 [x] XOR XOR m, #n4 ... 220 r, m ... 219 h ... 253 DBF, p ... 240 [S] SKE SKF SKGE SKLT SKNE SKT ST STOP SUB SUB SUBC SUBC m, #n4 ... 223 m, #n ... 221 m, #n4 ... 224 m, #n4 ... 224 m, #n4 ... 223 m, #n ... 221 m, r ... 228 s ... 253 m, #n4 ... 211 r, m ... 209 m, #n4 ... 214 r, m ... 212 addr ... 246 @AR ... 247 addr ... 243 @AR ... 243 [R] RET ... 249 RETI ... 250 RETSK ... 249 RORC r ... 226 m, #n4 ... 201 r, m ... 198 m, #n4 ... 205 r, m ... 203 m, #n4 ... 218 r, m ... 217 [P] PEEK POKE POP PUSH PUT WR, rf ... 238 rf, WR ... 239 AR ... 237 AR ... 235 p, DBF ... 241 [O] OR OR m, #n4 ... 216 r, m ... 216
270
APPENDIX F ORDERING MASK ROM
1 2
After developing the program, place an order for the mask ROM version, according to the following procedure: (1) Make reservation when ordering mask ROM. Advise NEC of the schedule for placing an order for the mask ROM. If NEC is not informed in advance, ontime delivery may not be possible.
3 4 5
(2) Create ordering medium.
6
Use UV-EPROM to place an order for the mask ROM. Add /PROM as an assemble option of the Assembler (AS17K), and create a mask ROM ordering HEX file (with extender for .PRO). Next, write the mask ROM ordering HEX file into the UV-EPROM. Create three UV-EPROMs with the same contents. (3) Prepare necessary documents. Fill out the following forms to place an order for the mask ROM: * Mask ROM ordering sheet * Mask ROM ordering check sheet
7 8 9 10 11
(4) Ordering
12
Submit the media created in (2) and documents prepared in (3) to NEC by the specified date.
13
Caution For details, refer to information document ROM Code Ordering Procedure (IEM-1366).
14 15 16 17 18 19 20
271
[MEMO]
272
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Tel.
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